Verilog : Module parameter, code simulates but doesn't synthesize

Question

I am facing a few issues in synthesizing some Verilog code - although the simulations seems to be fine.

Specifically, a module defined as follows..

module nexys2_sevensegment(
  input clk,
  input [NUM_CHARS*4-1: 0] disp_chars,
  output [NUM_CHARS-1: 0] anodes,   // The common cathodes for each display.
  output [6: 0] cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  parameter NUM_CHARS = 4; // The number of characters that need to be
                           // displayed. Should be in [1, 4].

And instantiated as follows,

  nexys2_sevensegment #(4) seven_seg_disp(clk, disp_bus, an, seg);

The simulation seems to be working fine, but when I synthesize it I get the following error:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "nexys2_sevensegment.v" in library work
ERROR:HDLCompilers:28 - "nexys2_sevensegment.v" line 8 'NUM_CHARS' has not been declared
ERROR:HDLCompilers:28 - "nexys2_sevensegment.v" line 9 'NUM_CHARS' has not been declared
Compiling verilog file "tb_nexys2_seven_segment.v" in library work
Module <nexys2_sevensegment> compiled
Module <tb_nexys2_seven_segment> compiled
Analysis of file <"tb_nexys2_seven_segment.prj"> failed.

I am working on Xilinx with a Spartan3e-1200 - Digilent Nexys2.

Thanks !

Marty · Accepted Answer · 2012-05-22 17:36:27Z

5

If you're using a parameter, you'll have to declare before you use it. Try:

module nexys2_sevensegment
  #( parameter NUM_CHARS=4 )
  (
  input clk,
  input [NUM_CHARS*4-1: 0] disp_chars,
  output [NUM_CHARS-1: 0] anodes,   // The common cathodes for each display.
  output [6: 0] cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  // ( remove parameter statement here )

Now the compiler has encountered a definition of NUM_CHARS before it sees it in the port definitions.

You may need to set a Verilog-2001 switch on you compiler for this to work.

answered May 22, 2012 at 17:36

Marty

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user597225 · Accepted Answer · 2012-05-23 01:26:59Z

4

You may also use port declarations after the port list:

//non-ANSI style header
module nexys2_sevensegment(
  clk,
  disp_chars,
  anodes,   // The common cathodes for each display.
  cathodes // The seven segments in the form {G,F,E,D,C,B,A}
  );

  parameter NUM_CHARS = 4; // The number of characters that need to be
                           // displayed. Should be in [1, 4]

  input                     clk;
  input  [NUM_CHARS*4-1: 0] disp_chars;
  output [NUM_CHARS-1: 0]   anodes;   // The common cathodes for each display.
  output [6: 0]             cathodes; // The seven segments in the form {G,F,E,D,C,B,A}

endmodule

answered May 23, 2012 at 1:26

user597225

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