synthesizable way to load initial values in verilog

Question

I would like to write a module that uses some coefficients that are loaded from a file.

For example:

reg [3:0]  coeffs[0:1];
reg  [6:0]   ans;
always @(posedge clk) begin
    if (!reset) begin
        coeffs[0] <=  3;
        coeffs[1]  <=  2;
        ans   <=   0;
    end
    else begin
        ans    <=   coeffs[0] *  coeffs[1];
    end
end

I would like to replace the values 3 and 2 by values that I can modify in a file, and provide the file during synthesis. Obviously, this file will only assign initial values to the registers. I don't want it to be a block ram, I want it to be like independent registers.

Just to clarify, I need the solution to be very generic, because I intent to use it in many modules that are doing the same thing, but with a different number of coefficients.

Meaning, in the end I wish to have a generic module that receives as a parameter a file name that stores the coefficients, and the number of coefficients and their width, and generates a code using those parameters.

I have tried readmemh but I understood it is only synthesizable to initiate a memory.

Any suggestions? Thanks.

Matthew · Accepted Answer · 2018-06-21 16:26:26Z

0

Here's a suggestion: put the statements initialising the array coeffs in an include file, eg

coeffs.v:

coeffs[0] <=  3;
coeffs[1] <=  2;

code:

reg [3:0]  coeffs[0:1];
reg  [6:0]   ans;
always @(posedge clk) begin
    if (!reset) begin
        `include "coeffs.v"
        ans   <=   0;
    end
    else begin
        ans    <=   coeffs[0] *  coeffs[1];
    end
end

An include file is included at compile time. So, your synthesiser will insert the contents of the file in the right place in the design. You could then manage the files using your operating system.

answered Jun 21, 2018 at 16:26

Matthew

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1 Comment

shush Over a year ago

The problem is that i wish to have a generic module, that receives as a parameters a file name, number of coefficients, and width. How can i use include file in that way?

Oldfart · Accepted Answer · 2018-06-21 16:39:04Z

0

I am happy to stand corrected, but apart from 'Trickery' (Include files, define files, running a script generating such before synthesis) I am not aware of any method where you can load plain numbers from a file for synthesis.
I admit it a is problem waiting for a solution.

_{If only to prevent major embarrassment when your chip comes back from the manufacturer and you find the boot-rom is completely empty.... As if that ever happened where I worked (rolls eyes) Fixing requires only a single (contact) layer change but the lower layer masks are the most expensive).}

answered Jun 21, 2018 at 16:39

Oldfart

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Comments

Eddy Yau · Accepted Answer · 2018-06-22 05:52:22Z

0

Using parameter to pass the initial value is better option.

 module A
    #( parameter INITIAL_VALUE_COEFFS_0 = 3,
       parameter INITIAL_VALUE_COEFFS_1 = 2)
     ( /* ignore it */ );
    reg [3:0]  coeffs[0:1];
    reg  [6:0]   ans;
    always @(posedge clk) begin
        if (!reset) begin
            coeffs[0] <=  INITIAL_VALUE_COEFFS_0;
            coeffs[1] <=  INITIAL_VALUE_COEFFS_1;
            ans       <=  0;
        end
        else begin
            ans       <=  coeffs[0] *  coeffs[1];
        end
    end
endmodule

answered Jun 22, 2018 at 5:52

Eddy Yau

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2 Comments

shush Over a year ago

I don't think using parameter is a good choice for me, as i would like to keep the number of coeffs as variable. meaning i would use a parameter for the number of coefficients, and i will use a generate block to declare and use the coefficients. There is no way to do that and to deliver the coefficient's values via parameter, right?

Eddy Yau Over a year ago

It is bad to use include file in the code.It is because if the module instantiate more than one time, you cannot find another way to apply different INITIAL value except duplicate the module.

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