VHDL unconstrained std_logic_vector - detection of increasing/decreasing index

Question

With an unconstrained std_logic_vector port on a component, it will follow the signal declaration from the higher level entity where the component was instantiated (if the signal is (n downto 0), the port will obviously match this).

However, if assigning a constant vector ("10100001" or x"A1" for example) to the port on the instantiation, the port will automatically default to "0 to 7" instead of "7 downto 0". Is there any way to "detect" that a unconstrained std_logic_vector is in the increasing/decreasing index format, so I can appropriately flip the bits if necessary?

Supply the constraint in association. IEEE Std 1076-2008 5.3.2.2 Index constraints and discrete ranges, paragraph 6 e) listed in subparagraph 3). Also 16.2.3 Predefined attributes of arrays, 6.5.7.3 Port map aspects ,6.5.6.3 Port clauses. Here use a qualified expression (9.3.5) subtype desc8 is std_logic_vector(7 downto 0); in a port association formal => desc8'(x"A1") and using last part of the rule in 5.3.2.2 e) 2) to specify the subtype. Provide a minimal reproducible example, particularly demonstrating a perceived need to flip bits, see 6.6.2 Object aliases c) 2). — user1155120
– user1155120, Commented Feb 24, 2021 at 19:49

adg6 · Accepted Answer · 2021-02-24 20:23:21Z

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The VHDL attribute 'ascending does what I want. So "My_Signal'ascending" will return a boolean true if the vector is in "0 to n" format, false if "n downto 0" format.

answered Feb 24, 2021 at 20:23

adg6

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Jim Lewis · Accepted Answer · 2021-02-26 20:56:04Z

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First be careful with unconstrained arrays on components as some synthesis tools may not support this feature, however, for testbenches it is just fine.

Next, rather than being concerned about ascending or descending ranges, instead you should normalize the ranges. You can do this with an alias:

entity fred is
port (
  Unconstrained_Port : std_logic_vector ; 
  . . . 
) ; 
end entity fred ; 
architecture one of fred is 
  alias Constrained_Port : std_logic_vector(Unconstrained_Port'length -1 downto 0) is Unconstrained_Port ;

answered Feb 26, 2021 at 20:56

Jim Lewis

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