VHDL - How to detect change on std_logic_vector?

Question

I have a std_logic_vector and I need to know when some changes occur on it. So far I wrote this:

process (cp, l1)
begin
    if rising_edge(cp) then
        rL1 <= l1;
    end if;
end process;
tickL1 <= rL1 xor l1;

rL1 is delayed version of l1, and l1 is the std_logic_vector I'm checking for changes. The problem is that xor returns std_logic_vector, but I need just 0 or 1. How can I get that?

This is not entirely clear. Do you want to know when it's changing or what changes? — Sebastian
– Sebastian, Commented Apr 28, 2012 at 15:01

Paul S · Accepted Answer · 2012-04-28 18:00:07Z

9

Why has everyone got an obsession with XOR?

changed <= '0' when rL1 = l1 else '1';

answered Apr 28, 2012 at 18:00

Paul S

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4 Comments

xx77aBs Over a year ago

Hahah thx :D I tried just "changed <= rL1 = l1" but that didn't work because = returns boolean and not std_logic. Also I forgot about "when" :)

Aleh Douhi Over a year ago

Won't such implementation lead to frequency lose and increasing of source usage comparing to xor implementation?

Paul S Over a year ago

@AlehDouhi what do you think an equality comparison will synthesise to? Probably an XOR and an OR reduce. So you'll probably get the same thing, but you might get some smaller, faster method that you hadn't thought of. Rule 1 of readable code, say what you mean and only optimise when necessary. Rule 1 of fast code, say what you mean and don't limit the compiler/synthesiser into one (and only one) implementation.

Aleh Douhi Over a year ago

Don't know, probably AND, NOT, comparators and MUX :) Sorry, just kidding :) Thank you for explanation!

Sebastian · Accepted Answer · 2012-04-28 15:14:04Z

3

You can use

change <= or_reduce(tickL1)

or

change <= or_reduce(rL1 xor l1);

Which OR's all signals of the result together, so if any of these is 1 the signal change will also be 1.

Edit: All of these reduce functions are in ieee.std_logic_misc.all

edited Apr 28, 2012 at 15:14

answered Apr 28, 2012 at 15:06

Sebastian

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2 Comments

xx77aBs Over a year ago

When I use or_reduce I get "Undefined symbol 'or_reduce'". Can you tell me what should I include ?

Sebastian Over a year ago

You have to use ieee.std_logic_misc.all.

Gustavo Vargas · Accepted Answer · 2012-04-28 15:04:41Z

0

You can try:

process (cp, l1)
begin
    if rising_edge(cp) then
        rL1 <= l1;
    end if;
end process;
changed <= '0' when (rL1 xor l1) = (others => '0') else '1';

In this case changed is a single bit.

I don't really remember if you can use the others operator inside a condition... that's the reason I said "you can TRY"... So, let me know if it works for you....

answered Apr 28, 2012 at 15:04

Gustavo Vargas

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1 Comment

xx77aBs Over a year ago

Unfortunatel this doesn't work (Error: Can not determine the "others" values in aggregate. (LRM 7.3.2.2)).

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