I have a following piece of code:

module cw305_reg_aes #(
   parameter pADDR_WIDTH = 21,
   parameter pBYTECNT_SIZE = 14,
   parameter pPK_WIDTH = 800 // 800 * 8
)(
   input  wire                                  usb_clk,
   input  wire                                  crypto_clk,
   input  wire [pADDR_WIDTH-pBYTECNT_SIZE-1:0]  reg_address,

   input  wire [pBYTECNT_SIZE-1:0]              reg_bytecnt,

   output reg  [7:0]                            read_data,
   input  wire [7:0]                            write_data,
   input  wire                                  reg_read,
   input  wire                                  reg_write,

   output wire [7:0]                            reg_pk
);

reg  [7:0]                   reg_read_data;
reg  [7:0]                   reg_crypt_public_key [pPK_WIDTH-1:0];
(* ASYNC_REG = "TRUE" *) reg  [7:0] reg_crypt_public_key_crypt [pPK_WIDTH-1:0];

always @(posedge crypto_clk) begin
   for (i=0; i<pPK_WIDTH;i=i+1) begin
      reg_crypt_public_key_crypt[i] <= reg_crypt_public_key[i];
   end   
end

assign reg_pk = reg_crypt_public_key_crypt[0]

always @(*) begin
   if (reg_read) begin
      case (reg_address)          
         `REG_CRYPT_PUBLIC_KEY:      reg_read_data = reg_crypt_public_key[reg_bytecnt];
         default:                    reg_read_data = 0;
      endcase
   end
   else
      reg_read_data = 0;
end

always @(posedge usb_clk) begin
   if (reg_write) begin
      case (reg_address)
         `REG_CRYPT_PUBLIC_KEY:      reg_crypt_public_key[reg_bytecnt] <= write_data;
      endcase
   end
end

How can I see if Vivado 2021.1 inferred block ram instead of distributed ram for the reg_crypt_public_key array?