VHDL error can't infer register because its behavior does not match any supported register model

Question

I am new to VHDL and trying to make a delay/gate application for programmable FPGA, with adjustable lenght of delay and gate output. As soon as the input signal is recieved, the thing should ignore any other inputs, until generating of gate signal is finished.

I want to use this component for 8 different inputs and 8 different outputs later, and set desired delay/gate prameters separately for each one by means of writing registers.

When trying to compile in Quartus II v 11.0 i am getting this error:

Error (10821): HDL error at clkgen.vhd(46): can't infer register for "control_clkgen" because its behavior does not match any supported register model

And as well

Error (10822): HDL error at clkgen.vhd(37): couldn't implement registers for assignments on this clock edge

No idea whats wrong, here is the code of the component:

library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;


ENTITY clkgen is
port(
 lclk                         : in  std_logic;
start_clkgen           : in  std_logic;
gate_clkgen            : in std_logic_vector(31 downto 0);
 delay_clkgen           : in std_logic_vector(31 downto 0);
 output_clkgen          : out std_logic

 );
END clkgen ;


ARCHITECTURE RTL of clkgen is

 signal  gate_cycles_clkgen    : std_logic_vector(32 downto 0);
 signal  delay_cycles_clkgen    : std_logic_vector(32 downto 0);
 signal  total_cycles_clkgen    : std_logic_vector(32 downto 0);
 signal  counter_clkgen         : std_logic_vector(32 downto 0);
 signal  control_clkgen         : std_logic;



begin
 gate_cycles_clkgen    <= '0' & gate_clkgen;
 delay_cycles_clkgen    <= '0' & delay_clkgen;
 total_cycles_clkgen    <= gate_cycles_clkgen + delay_cycles_clkgen;


 start_proc: process(lclk, start_clkgen)
  begin
   if (start_clkgen'event and start_clkgen = '1') then
    if control_clkgen = '0' then
     control_clkgen   <= '1';
    end if;
   end if;  

   if (lclk'event and lclk = '1') then
    if control_clkgen  = '1' then
     counter_clkgen <= counter_clkgen + 1;
    if (counter_clkgen > delay_cycles_clkgen - 1 AND counter_clkgen < total_cycles_clkgen + 1) then
     output_clkgen <= '1';
    elsif (counter_clkgen = total_cycles_clkgen) then
     counter_clkgen   <= (others => '0');
     output_clkgen    <= '0';
     control_clkgen   <= '0';
    end if;
   end if;
 end if;
 end process start_proc;

END RTL;

Big thanks in advance for help.

Josh · Accepted Answer · 2012-06-25 10:55:02Z

2

The problem is that in the way you has described the element control_clkgen - it is edge sensitive to two different signals (lclk, and start_clkgen). What the tools are telling you is that "hey, as I am trying to make your valid VHDL design fit into a real piece of hardware, I have found that there are not any pieces of hardware that can implement what you want. Basically, there are no flip flops that can be edge sensitive to two signals (only one, typically the clock.

Possible solution: Do you really need control_clkgen to be sensitive to the edge of start_clkgen? Would it be good enough, or could you find another solution where start_proc is sensitive only to lclk and you simply check if start_clkgen is high?

start_proc: process(lclk)
   begin
      if (rising_edge(lclk)) then
          start_clkgen_d <= start_clkgen;
          if (start_clkgen='1' and start_clkgen_d='0') then
             if control_clkgen = '0' then
                control_clkgen   <= '1';
             end if;
          end if;
      end if;
      ...

answered Jun 25, 2012 at 10:55

Josh

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3 Comments

Paul Seeb Over a year ago

Just want to point one thing out. You should almost NEVER use a rising edge statement on anything besides an actual clock. Implementation on chips has to use clock domains so associating a rising edge statement with a non clock domain signal will give you skew warnings. The "best method" is to create a "tick signal" by registering the signal you are checking and doing something like tick <= reg_sig xor sig and checking when tick is high under a synchronous block inside rising edge clock statement

Josh Over a year ago

I will add that my assumption above is that lclk is a true clock.

David Hons Over a year ago

Thank you very much for the simple and clear explanation Josh, that helped a lot with understanding how things work. lclk is indeed linked to true clock of the board. At the moment i got it working by simply checking if input signal is true, as you suggested ( i have adjustable pulser i can use to test it ). My next step will be registering the input signal as Paul Seeb suggested, so i dont miss too short input signals.

bmk · Accepted Answer · 2012-06-25 10:52:54Z

1

You are describing a register control_clkgen which has two clocks start_clkgen and lclk. I guess that's not supported by your synthesis tool. You have to describe this behavior in another way. Maybe use start_clkgen as asynchronous or synchronous preset signal or combine those two signals into one single clock signal or use more than one flipflop for that functionality.

answered Jun 25, 2012 at 10:52

bmk

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