How to monitor signal in SystemVerilog program block

Question

I'm trying to learn few things about testbenches with SystemVerilog. However I couldn't seem to find a way to monitor DUT signal inside program block

Consider following example. Signal 'dummy' is output of DUT and input to program block. Now I need to monitor 'dummy' in program block to raise a flag 'test' when 'dummy' has particular value.

In general module-driven testbench, I would simply write always @(dummy), but always blocks are not allowed under program. How would I achieve this?

I remember that someone said the program block has some issue and do not really suggest to use it. — Enze Chi
– Enze Chi, Commented Aug 1, 2012 at 23:21
@EnchanterThunderbird can you state some references about this issues? — e19293001
– e19293001, Commented Sep 1, 2012 at 7:53
See go.mentor.com/programblocks for recommendations on avoiding program blocks. — dave_59
– dave_59, Commented Oct 10, 2013 at 3:01

dwikle · Accepted Answer · 2012-07-31 19:37:35Z

6

You can write sequential code like this:

program test(input dummy);
  initial begin
    ...
    wait(dummy == <something>);
    ...
    @(posedge dummy);
    ...    
  end
endprogram

Or you could emulate an always construct using a forever loop.

program test(input dummy);
  initial begin
    forever begin
      @(posedge dummy);
      if (dummy == <something>) ...
    end 
  end
endprogram

answered Jul 31, 2012 at 19:37

dwikle

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1 Comment

wisemonkey Over a year ago

awesome I can add wait under fork-join so TB can work properly through general execution as well as I can check the signal required

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