Pythonesque bit-slicing in Verilog?

Question

In Python, I can select even or odd bits like this:

>>> bits = ['a','b','c','d'];
>>> bits[0::2]
['a', 'c']
>>> bits[1::2]
['b', 'd']

It would be very practical if I could do this in Verilog, so that I wouldn't have to expand the expression and do it manually. Expanded (i.e. {a[0], a[2]} and {a[1], a[3]}), it obviously wouldn't work with my otherwise parameterized wire set.

dwikle · Accepted Answer · 2012-12-22 03:16:01Z

2

There is no mechanism in Verilog or SystemVerilog to do a bit slice like the Python example you gave. That is, you cannot specify a step of 2 between bits.

You can do this with a for-loop, and it doesn't need to be in a generate block like in your own answer.

Modified example from your answer:

always @(*) begin
   for (int i = 0; i < FLOORS; i++) begin
      RELEVANT[i] <= FLOOR_REQUEST[i*2+FORWARD];
   end
end

This should synthesize okay as long as FLOORS is a constant.

answered Dec 22, 2012 at 3:16

dwikle

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2 Comments

Janus Troelsen Over a year ago

Wouldn't this solution require that RELEVANT is a reg? Would it synthesize to a flip-flop in this case?

dwikle Over a year ago

It would need to declared as a reg type, but that does not automatically mean it will synthesize to a flop. In this case it would not.

Janus Troelsen · Accepted Answer · 2012-12-22 01:08:29Z

1

It can be done with a generate block. Example:

wire [FLOORS-1:0] RELEVANT;

genvar i;
generate
    for (i=0; i<FLOORS; i=i+1) begin
        assign RELEVANT[i] = FLOOR_REQUEST[i*2+FORWARD];
    end
endgenerate

FLOORS is the width of the output wire (half the width of the input wire).
RELEVANT is the result.
FORWARD is the even/odd selector (0 or 1).
FLOOR_REQUEST is the input.

answered Dec 22, 2012 at 1:08

Janus Troelsen

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