module circuit_1 (a, b, c);
input [1:0J a,b;
output [3:0J c;
assign c = a + b;
If input a = 2'b11 and input b = 2'b10,
what value would output c have ? Please give a descriptive answer.
Also kindly tell me functionality of assign and always. I am a bit confused.
c = 4'b0101 // Output, implicitly a wire
"assign" is used for net type declarations(Wire,Tri etc).Since wires change values according to the value driving them, whenever the operands on the RHS changes,the value is evaluated and assigned to LHS(simulating a wire)
always - is used for registers + combinational logic. If it is always(@ posedge clk)- The event posedge clk triggers the always block and the logic inside the block is evaluated and assigned.
always @ (*) - If something in the RHS of the always block changes,that particular expression is evaluated and assigned.
Imagine assign as wires and always blocks as registers (For now) , as their behavior is same.
always @* is for reg types not registers, assign implies the same combinatorial logic as always @*. always @(posedge clk) implies flip-flops (registers).
assign implies the same combinational logic as always @* why do I have to use reg-variables for the always-block and wires for the assign? Why can't I use the wires for the always-block too?logic instead, for all uses except multi driven wires. I think this is a pretty good answer: stackoverflow.com/a/33462996/97073 An external reference: blogs.mentor.com/verificationhorizons/blog/2013/05/03/…c = 0101, actually c[2:0] become 101 but extension of 0 takes place as c is a 4 bit data.
