Verilog assignments in a sequential always

Question

I know that I should be using a non-blocking assignments in sequential always assignments. However, I accidentally happen to use a blocking assignment in part of my code, here it is:

reg tb_strobe = 0;
reg [9:0] tb_strobe_cnt = 0;
reg tb_sync = 0;

always@(posedge tb_clkh)
begin
    if (~tb_resetl) begin
        tb_strobe     <= 0;
        tb_strobe_cnt <= 0;
        tb_sync     <= 0;
    end
    else begin

        if (tb_strobe_cnt == 1022) begin
            tb_strobe <= 1;
            tb_strobe_cnt <= tb_strobe_cnt + 1;
        end else if (tb_strobe_cnt == 1023) begin
            tb_strobe <= 0;
            tb_strobe_cnt <= 0;
        end else begin
            tb_strobe <= 0;
            tb_strobe_cnt <= tb_strobe_cnt + 1;
        end

        if (tb_strobe == 1) begin
            tb_sync = 1;             //  <-- this is the mistakenly used blocking assignment
        end else begin
        end

    end
end

And then my simulator behaves unpredictably, and once I fixed that assignment to be a non-blocking one, it started working fine !!!!

I am curious as to what was wrong with the above (in my specific code)? In the way that I used it, since I am only calling tb_sync once in my code, I wasn't expecting any unpredictable behavior... And tb_sync is not being assigned anywhere else in the code. Any idea what is wrong?

dave_59 · Accepted Answer · 2015-02-21 19:13:20Z

1

Non-blocking assignments are used to prevent race conditions between multiple processes that write and read the same variable on the same clock edge. It just takes one process that writes, and another process that reads the same variable on the same clock edge to create that race. Your example does not show the process that reads tb_sync, but I'm assuming that's where the race is.

answered Feb 21, 2015 at 19:13

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

Rudy01 Over a year ago

Perfect explanation. It makes lots of sense. Yes in another process, I am reading "tb_sync", and that is exactly the problem. Because on the same clock edge one of them writes and the other reads. However, when I make it non-blocking, the write process will not happen until the end.

Collectives™ on Stack Overflow

Verilog assignments in a sequential always

1 Answer 1

1 Comment

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

1 Comment

Your Answer

Sign up or log in

Post as a guest

Related