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I'm working on a project on the Nexys 3 FPGA, written in Verilog on Xilinx, that requires some file input and output (to the computer that just programmed the FPGA, preferably.) Using the program Adept, you can write to some specific address of one of the FPGA memories. You also can read from specific addresses in the same memory-space.

This could be the perfect solution to my problems - but how do you access these memories using Verilog?

For example: In state S2, I want to read in the memory at location 00000 (which I had previously loaded using Adept while I was still in step S1.) How do I access this data, process it, and then rewrite a different section of the memory? Thanks in advance.

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As I remember it, Adept works "outside" the usual FPGA logic, accessing the RAMs over JTAG. It will presumably map them as one big "lump" - you'll have to read the documentation to find out which order the RAMs are accessed.

If you want to access them from Verilog, you first need to instantiate (ie directly write some code which says "use a ram block like this") or infer a block of RAM (write code which "looks" like the behaviour of a RAM clock - the tools will then figure it out). If you read the documentation for the synthesiser it will describe both approaches.

Then your logic can control the data, address and control lines of the RAM to read and write from and to it.

Once you can make a RAM, and know which of the many blocks of RAM you are writing to with Adept, you will then have to make sure the FPGA build tools put your RAM block in the right place so that you are accessing the right one with Adept. Either that or each time you build the FPGA you'll hav eto check where it went and change your Adept setup to access a different RAM... are you sure this is the best way to comunicate with your FPGA?

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Thanks, I figured I would have to do something rather complicated to set up RAM in my code, but how do I coordinate the addresses between the Adept manual memory writing and the Verilog synthesized memory access?
I have never use adept to access memory, but I assume it access the memory just like your verilog code should, and the locations should be the same.
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The board has different types of memory, which one you are writing to? Are you writing to the memory inside the FPGA or one of the memories on the board? Nexyx 3 has these 3 memories on board:

  • 16Mbyte Micron Cellular RAM
  • 16Mbyte Micron Parallel PCM
  • 16Mbyte Micron Quad-mode SPI PCM

some are easy to access some are more difficult, if you clarify which one you want to access, it will be easier to answer to your question.

You maybe able to find help from the example file from Nexys 2:

"EDK project that demonstrates how to connect the BSB shared buses through I/O multiplexers, allowing access to both RAM and FLASH memories on the Nexys2-500. Made using EDK 11." You can find the files here: http://www.robotshop.com/content/ZIP/nexys2-500-edk-11-ram-flash-nexys2-500k.zip

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Thanks, I believe I was writing to the 16MB RAM, although Adept has options to write to the other ones (if those are easier to implement in the code.) The sample project is very helpful, I'll see if I can figure out a solution from it.

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