I have to take the internal clock which is already generated in fpga and I have to give it to an output variable. How can ı get that internal clock with verilog code? someone told me that fpga board generate 100MHz internally. How can i get that clock signal to my verilog code ?
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3This may be better-suited for electronics.stackexchange.com.Oliver Charlesworth– Oliver Charlesworth2013-05-27 10:37:36 +00:00Commented May 27, 2013 at 10:37
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1It could help if you tell us what is your board, what FPGA you are using. Your question is also not clear what you exactly asking, getting a locally generated clock is as easy as just connecting the output of the block that creates the clock to the clock input of your design, but if you want to generate a different frequency, then it depends on the type of FPGA you have and the input frequency of your clock before creating the 100MHz to be generated.FarhadA– FarhadA2013-05-28 10:17:12 +00:00Commented May 28, 2013 at 10:17
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2 Answers
Your question ins't totally clear, but it sounds like you've got an internally generated clock on an fpga, which is not 100 MHz and you'd like to generate a 100 MHz clock from said internally generated clock? I have a hard time believing that you really have an internally generated clock within your fpga (I'll bet you have an external oscillator that is connected to your fpga). That stated almost all the fpgas (I'd bet all fpgas -- haven't heard of a modern one without) have some clock multiplier circuitry, which allows you to take a clock input and manipulate it (e.g. change frequency, phase, polarity, etc, etc). On xilinx fpgas this block is called a DCM and is easily configured via coregen. If you provide more specifics/clarity I'm sure people can help you get what you're looking for.
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You can use the PLL module (which you generate through FPGA synthesis tool). Here this PLL can take 1 input CLOCK and can able to produce upto 5 OUTPUT clock. Now you assign any of the output clock signal to your main design(i,e. DUT)
