How to reuse an instantiated module in verilog with updated inputs

Question

I have a module :

module abc(
  input  in1,
  input  in2,
  output in3
);

Instantiating this module in another main module:

abc name_abc(in1, in2, out);

Now in1 is changed based on some other signal. From what I understand, the instantiation would have created a block of the logic, now I want to use the block already created but with different inputs or updated inputs. Is there a way to do this in verilog?

What I want to do is :

abc name_abc(in1_updated, in2, out);

Morgan · Accepted Answer · 2013-08-04 06:55:54Z

7

Inputs are continuous time signals. The module instantiation is not a method call but constantly executing logic, therefore any change in in1 value will be passed directly to instance name_abc.

If you mean to use the same module (hardware) but being able to switch between 2 data streams, imply a mux in front of it.

wire   connect_to_abc_in;
assign connect_to_abc_in = (select) ? in1 : in1_alternative ;

edited Aug 4, 2013 at 6:55

answered Jul 31, 2013 at 8:02

Morgan

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3 Comments

Morgan Over a year ago

@Preets if you have already learnt to program the shift to HDLs (Verilog/VHDL) can be pretty jarring, syntax can be familiar but meaning and implication is very different. Persevere and try to enjoy learning new skills.

Victor L Over a year ago

Here is the complete code for the answer on EDA Playground. However, I'm not sure why Icarus Verilog is giving a implicit definition of wire logic warning. I don't see a warning with VCS.

e19293001 Over a year ago

@VictorLyuboslavsky, you've got a typo error in connet_to_abc_in.

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