Concatenating bits in VHDL

Question

How do you concatenate bits in VHDL? I'm trying to use the following code:

Case b0 & b1 & b2 & b3 is ...

and it throws an error

Thanks

user21246 · Accepted Answer · 2008-10-16 17:16:38Z

27

The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only

answered Oct 16, 2008 at 17:16

user21246

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Martin Thompson Over a year ago

It works for variable assignments := as well.. see other answers

Justin · Accepted Answer · 2009-12-01 15:08:05Z

13

You are not allowed to use the concatenation operator with the case statement. One possible solution is to use a variable within the process:

process(b0,b1,b2,b3)
   variable bcat : std_logic_vector(0 to 3);
begin
   bcat := b0 & b1 & b2 & b3;
   case bcat is
      when "0000" => x <= 1;
      when others => x <= 2;
   end case;
end process;

answered Dec 1, 2009 at 15:08

Justin

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musicakc · Accepted Answer · 2014-09-14 18:41:51Z

12

Here is an example of concatenation operator:

architecture EXAMPLE of CONCATENATION is
   signal Z_BUS : bit_vector (3 downto 0);
   signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
begin
   Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT;
end EXAMPLE;

edited Sep 14, 2014 at 18:41

musicakc

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answered Oct 16, 2008 at 17:23

user21246

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