How does the shift register work in binary to bcd conversion

Question

I found this code for a 12 bit binary to bcd conversion but I can't seem to understand the shift register part (just showing the state machine part). I need help in understanding how exactly the '&' works in a shift register and if someone can also produce a different way for the shift register part to look something like the code below as it is easier to understand the flow of data:


    ishiftRegister(7) <= Rxd;

    ishiftRegister(6 downto 0) <= iShiftRegister(7 downto 1);


     -- State Machine
    process(present_state, binary, binary_in, bcd_temp, bcds_reg, shift_counter)
    begin
        next_state <= present_state;
        bcds_next <= bcd_temp;
        binary_next <= binary;
        shift_counter_next <= shift_counter;

        case present_state is

            when st_start =>
               next_state <= st_shift;
               binary_next <= binary_in;
               bcds_next <= (others => '0');
               shift_counter_next <= 0;

            when st_shift =>
                if shift_counter = 12 then
                    next_state <= st_stop;
                else
                    binary_next <= binary(10 downto 0) & 'L';
                    bcds_next <= bcds_reg(18 downto 0) & binary(11);
                    shift_counter_next <= shift_counter + 1;
                end if;

            when st_stop=>
                next_state <= st_start;

        end case;
    end process;

am9417 · Accepted Answer · 2019-04-16 10:48:35Z

0

The & is a concatenation operator. Check for example this question for more discussion: Concatenating bits in VHDL

bcds_next <= bcds_reg(18 downto 0) & binary(11);

With bcds_reg(18 downto 0) you take the 19 least significant bits of bcds_reg vector (and drop the most significant bit out). I.e. the register is shifted to the left. The binary(11) is the most significant bit of a 12-bit vector binary. Concatenating a 19-bit vector and a single bit with & creates you a 20-bit vector which you can then assing to the 20-bit vector bcds_next.

For your other question, I think the following would also be possible and an equal operation without the & operator.

bcds_next(19 downto 1) <= bcds_reg(18 downto 0);
bcds_next(0) <= binary(11);

answered Apr 16, 2019 at 10:48

am9417

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2 Comments

silverhawk Over a year ago

thanks for the reply , one more doubt about what does the & 'L' actually do?@am9417

am9417 Over a year ago

Also the binary register gets shifted. The left-most item was moved to that bcds_reg and the other bits are moved to the left, too. In order to keep the length of binary in 12, a value (in this case L) is appended to the right end of the vector. L stands for "Low":' It is neither 1 or 0, but a "weak signal that should probably go 0". In your design it's probably used just to fill the vector to have the desired length of 12, because the logic seems to ensure that this "L" value will never be used.

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