I have an application that uses Verilog and C (SystemC to be precise). I wanted to see if there was a way to have a common header file that can be used across the entire application ?
Such that:
#define FOO 4
doesnt have to be repeated in another verilog file
`define FOO 4
Some simulators will let you define macros from the command line during compile and pass the definition to SystemC and Verilog. Check with your simulators manual, it should look something like +define+FOO=4 of -defineall FOO=4 if it is supported.
The other approach is to create a script to that generates a converted header for you. This way you only maintain one file. This approach is better if you also want to share struct, typedef, and enum between SystemVerilog and SystemC.
I think they are different languages. It is hard to make common file to be used directly. But you can have a common source and use script to generate the header files for you.
