Array Type is not constrained - VHDL

Question

I wrote the test bench for the following vhdl code:

library ieee;
USE ieee.std_logic_1164.all;
---USE ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity division3 is
  port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));
  end division3;

  architecture arch_div3 of division3 is
             signal v_TEST_VARIABLE1 : integer;
             signal v_TEST_VARIABLE2 : integer;
                   begin 
      P3: PROCESS(num1, num2)
       variable n_times: integer:=1;
      begin

        if(num1>num2) then
       v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L1:loop
         n_times := n_times + 1;
        exit when ((v_TEST_VARIABLE2 -  v_TEST_VARIABLE1)>0);
        v_TEST_VARIABLE1 <= v_TEST_VARIABLE1 - v_TEST_VARIABLE2;
       end loop L1;


    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

   elsif (num2>num1) then
      v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ;  
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L2:loop
        n_times:=n_times+1;
       exit when ((v_TEST_VARIABLE1 -  v_TEST_VARIABLE2)>0);
       v_TEST_VARIABLE2 <= v_TEST_VARIABLE2 - v_TEST_VARIABLE1;

   quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

end loop L2;
    else
      quotient <= x"0001";
    end if;

  end PROCESS P3;
    end arch_div3;

The testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;

-- entity declaration for your testbench.Dont declare any ports here  
ENTITY division3_tb IS 
END division3_tb;

ARCHITECTURE behavior OF division3_tb IS
   -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT test  --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such. 
    port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));

    END COMPONENT;
   --declare inputs and initialize them
   signal num1 : std_logic_vector := "00000000";
   signal num2 : std_logic_vector := "00000000";
   --declare outputs and initialize them
   signal quotient : std_logic_vector(15 downto 0);
   -- Clock period definitions
   constant clk_period : time := 1 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
   uut: test PORT MAP (
         num1 => num1,
          num2 => num2,
          quotient => quotient
        );       

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
        num1 <= "00001000";
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        num1 <= "00001110";
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;
   -- Stimulus process
  stim_proc: process
   begin         
        wait for 7 ns;
        num2 <="00000001";
        wait for 3 ns;
        num2 <="00000010";
        wait for 17 ns;
        num2 <= "00000011";
        wait for 1 ns;
        num2 <= "00000110";
        wait;
  end process;

END;

On compilation I am getting the error in the architecture, saying:

** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(19): Array type for 'num1' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(20): Array type for 'num2' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(55): VHDL Compiler exiting

I am a bit new to VHDL. Can someone explain to me about the constraints on array type? Thanks.

Community · Accepted Answer · 2017-05-23 12:09:32Z

6

The range constrain is missing on the signal declaration based on std_logic_vector, so the declaration of num1 and num2 should be:

signal num1 : std_logic_vector(7 downto 0) := "00000000";
signal num2 : std_logic_vector(7 downto 0) := "00000000";

The reason is that the std_logic_vector type is declared without range as (VHDL-2002):

type std_logic_vector is array (natural range <>) of std_logic;

In some context it is legal to declare objects without range (called unconstrained), like function arguments and entity ports, but signals must be declared with explicit range (called constrained), since signals are potentially to be converted directly into wires in a design.

Btw. you may want to revisit some of the additional comments in my previous answer, since I can see that the division3 module may still have some room for improvement.

edited May 23, 2017 at 12:09

CommunityBot

11 silver badge

answered Jun 19, 2014 at 4:56

Morten Zilmer

15.9k4 gold badges35 silver badges52 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Array Type is not constrained - VHDL

1 Answer 1

Comments

Your Answer

Linked

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Linked

Related