vhdl ERRROR: Attribute "range" requires a constrained array prefix

Question

Two questions:

how to get rid of the warning: "Shared variables must be of a protected type." while keeping it as a "shared variable"?
How to fix Attribute "range" requires a constrained array prefix?

First of all, what is a constrained array prefix?


$ vcom.exe -2002 -l test3.vhd

** Warning: test3.vhd(14): (vcom-1236) Shared variables 
must be of a protected type.

** Error: test3.vhd(20): (vcom-14402) Attribute "range" 
requires a constrained array prefix.

library ieee;
use ieee.std_logic_1164.all;

entity test3 is
end entity;

architecture beh of test3 is
    constant dw    :integer := 8;
    constant depth :integer := 128;
    
    type mem_t is array (integer range<>) of std_logic_vector(dw-1 downto 0);
    
    shared variable ram_block :mem_t(0 to depth-1);    
begin

process 
     variable i:integer;
begin
     for i in mem_t'range loop
         report integer'image(i);
     end loop;
end process;

end architecture;

mem_t is an unconstrained type and hence the attribute 'range cannot be used. I suggest using ram_block as the prefix. — Tricky
– Tricky, Commented Mar 23, 2022 at 21:24
Lets be real clear. After VHDL-2000, shared variables of an ordinary type (such as your array of std_logic_vector) are illegal. So an appropriate message in this case would be Suppressed ERROR: test3.vhd(14): (vcom-1236) Shared variables must be of a protected type. It is deceptive by the tool vendor to issue it as a warning. — Jim Lewis
– Jim Lewis, Commented Mar 25, 2022 at 1:22
The fact that it is illegal is something that could be addressed in a future revision of the standard, but there would have to be someone willing to do the work to do the modifications - they would be numerous and tedious, but probably not too hard to do. In the past, I have invited parties who have used this illegally, but they have decided not to even show up. — Jim Lewis
– Jim Lewis, Commented Mar 25, 2022 at 1:25
If you would like to see an appropriate way to do this, please see my blog post at: osvvm.org/archives/1758 — Jim Lewis
– Jim Lewis, Commented Mar 25, 2022 at 1:27

Tricky · Accepted Answer · 2022-03-23 21:08:54Z

1

A protected type in VHDL, is similar to a class in OO programming, where it can have member methods and it can retain state. Since 2002, it is required that shared variables must be of a protected type. By default, most tools only throw a warning to maintain backwards compatibility unless you turn on strict rule checking

So you have two options to remove the warning

revert to VHDL 1993 standard.
Create a protected type.

Your example shows no need for a shared variable. It could be made into a normal (non shared) variable inside the process.

answered Mar 23, 2022 at 21:08

Tricky

4,6083 gold badges15 silver badges32 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

user16145658 Over a year ago

It could be made into a normal variable the previous answer does with it's silently added a wait statement to the process in his design that does nothing but illustrate lack of attention to detail or research effort. Poor quality questions will continue as long as you answer. In 1999 P1076a produced IEEE Std 1076a-2000 introducing protected types and requiring shared variables to be of protected types which are not synthesis eligible, providing exclusive access to variables through methods. This was incorporated into IEEE Std 1076-2000 which was not well received.

pico · Accepted Answer · 2022-03-23 19:26:15Z

0

Question 2, I found... But Question 1, I'm still not sure about..

architecture beh of test3 is
    constant dw    :integer := 8;
    constant depth :integer := 128;
    
    type mem_t is array (integer range<>) of std_logic_vector(dw-1 downto 0);
    
    shared variable ram_block :mem_t(0 to depth-1);    
begin

process 
     variable i:integer;
begin
    report "left:"  & integer'image( ram_block'left);
    report "right:" & integer'image( ram_block'right);   
    
    for i in ram_block'range loop
        report integer'image(i);
    end loop;
    
    wait;
end process;


end architecture;

answered Mar 23, 2022 at 19:26

pico

1,9507 gold badges36 silver badges68 bronze badges

Collectives™ on Stack Overflow

vhdl ERRROR: Attribute "range" requires a constrained array prefix

2 Answers 2

1 Comment

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

1 Comment

Comments

Your Answer

Sign up or log in

Post as a guest

Related