Unusual behavior of verilog code

Question

I am writing one simple asynchronous sequence detector, but i am getting unusual result at one point. Code is working fine with "assign a8 = ((y2&&inp1&&~inp2)||(y1&&inp1)); " but if i replace above line with following lines in my code its not giving the correct result.

assign a6 =  (y2&&inp1&&~inp2);
assign a5 = (y1&&inp1);
assign a8 = a6||a5;

Both are technically the same but i am not able to understand why output is not coming correct when i use above lines of code.

    module Async_Design(inp1,inp2,outp);
        input inp1,inp2;
        output outp;
        wire y1 ,y2;

    /*assign a6 =  (y2&&inp1&&~inp2);
    assign a5 = (y1&&inp1);
    assign a8 = (a6||a5);*/

    /*Uncommenting the above section and commenting below 
line is not giving correct result*/
       assign a8 =  ((y2&&inp1&&~inp2)||(y1&&inp1));    
        Delay D1(y1,a8);

        nand(a1,y1,1'b1);
        nand(a2,a1,inp1);
        nand(a3,a2,1'b1);
        nand(a4,a3,inp2);
        nand(a5,a4,1'b1);

        Delay D2(y2,a5);

        assign outp = y1;

    endmodule

    module Delay(q,inp);

        output q;
        input inp;
        reg q;
        initial
        begin
            q=1'b0;
        end
        always @(*)
        begin
            q=((inp&&1'b1)||(inp&&1'b1));
        end

    endmodule 

/***********************************************/
TEST BENCH
/***********************************************/

    module Async_Design_Test;

    reg  inp1,inp2;
    wire outp;
    reg[15:0] sequence1;
    reg[15:0] sequence2;
    integer i;

    Async_Design Async(inp1,inp2, outp);

    initial
    begin

        sequence1 = 16'b 0101_1111_0111_1111;
        sequence2 = 16'b 1010_1010_1110_1111;


       for( i = 0; i <= 15; i = i+1)
       begin
          inp1 = sequence1[i];
            inp2 = sequence2[i];
            #6

            $display( " Input1 = ", inp1,  "  Input2 = ", inp2, "  Output = ", outp,);

       end
    end

    endmodule

Can anyone help me to understand this behavior as i am new to HDL coding

Side by side comparison on EDA Playground.

Morgan
– Morgan

2014-11-11 09:32:50 +00:00
Commented Nov 11, 2014 at 9:32 — Morgan
– Morgan, Commented Nov 11, 2014 at 9:32

Qiu · Accepted Answer · 2014-11-11 09:22:47Z

3

Your code after change is not valid one. Why?

assign a5 = (y1&&inp1);
...
nand(a5,a4,1'b1);

What you're trying to do is drive a5 wire in two different places (btw your compiler should print an error like "can't resolve multiple constant drivers for net a5"). And it won't work, since you can drive a wire only in one place. If you change one of this lines, e.g.:

assign a6 = (y2&&inp1&&~inp2);
assign a7 = (y1&&inp1);
assign a8 = (a6||a7);

you'll get the same output as if you use assign a8 = ((y2&&inp1&&~inp2)||(y1&&inp1)).

PS Consider usage of & and | operators.

answered Nov 11, 2014 at 9:22

Qiu

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