verilog code for a state machine

Question

I'm given a combinational circuit and I will design a verilog code for that circuit. It's about state machines. The equations are:

A(t+1)=A(t)+B(t);
B(t+1)=A(t)'+B(t);

There is no other outputs or inputs. I have tried few codes and they didn't work. I'm confused about assignig A,B,A_next,B_next as inputs,outputs and wires. Can anyone give me a little clue so that I can try it again?

module statemac_posed(clk,a,b);
input clk;
output a,b;
reg a_next,b_next;

always@(posedge clk)
begin
a=a_next;
b=b_next;
a_next=a|b;
b_next=~a|b;

end

endmodule

The circuit has 3 inputs (Ain, Bin, clock), 2 states (Ast, Bst) and 2 outputs (Aout, Bout), right? What does A(t)' mean ( ' )? — kestasx
– kestasx, Commented Dec 25, 2014 at 10:20
I should add that A_next is the input for the first DFF and so is B_next for the second DFF. — eslem ecrin
– eslem ecrin, Commented Dec 25, 2014 at 10:30
Then probably just declare 2 registers Ast and Bst in the module, make alwais block sensitive to clock and assign expressions to these registers, and assign these registers to outputs. If this dosn't work - please provide Your non-working code. — kestasx
– kestasx, Commented Dec 25, 2014 at 10:57
Should I assign expressions to registers and registers to outputs in the same begin-end block? — eslem ecrin
– eslem ecrin, Commented Dec 25, 2014 at 11:16

Morgan · Accepted Answer · 2014-12-25 16:35:19Z

The output from a flip-flop is your next value, as synchronous logic you could just write:

For FPGA intial can be used to set initial values for ASIC active low resets are used

module statemac_posed(
  input      clk,
  output reg a,
  output reg b
);

initial begin
  a = 'b0;
  b = 'b0;
end

//On clock edge update a &b with new values based on previous a & b value
always@(posedge clk) begin
  a <= a|b;  
  b <= ~a|b;
end

endmodule

This is equivalent to :

module statemac_posed(
  input      clk,
  output reg a,
  output reg b
);
  reg a_next;
  reg b_next;

//Combinatorial take outputs from flip-flops and combinatorial define next value
always @* begin
  a_next = a|b; 
  b_next = ~a|b;
end   

initial begin
  a = 'b0;
  b = 'b0;
end

//on Clock edge take the next values
always @(posedge clk) begin
  a <= a_next;
  b <= b_next;
end

endmodule

Any variable assigned to inside an initial or always needs to be of type reg. logic is also valid if using SystemVerilog. Not doing this was the cause of the errors you mentioned in comments.

This should give some insight into how to use verilog.
NB: use blocking (=) with combinatorial (@*). non-blocking (<=) with edge triggered (@(posedge clk)) to correctly describe hardware.

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