How does a state transition work with a Verilog FSM code-wise?

Question

In the code linked above, which is a standard Verilog FSM, I want to clear up exactly how the state transition works. The sequential portion of the code does the assigning for the next state, but my confusion is how does it go from that sequential section to selecting the proper next state from the combinational section of code?

Is it that at the clock edge, since the "current state" is being re-assigned a new value at the clock edge, it automatically triggers the sensitivity list in the combinational section of code, which is what then correctly selects the value of next state?

dave_59 · Accepted Answer · 2017-01-23 00:08:53Z

1

In your example, @(*) is equivalent to @(state or start or restart). So any change to one of those signals causes next_state to get re-evaluated.

answered Jan 23, 2017 at 0:08

dave_59

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Yuerno Over a year ago

Thanks for the response! So am I right in thinking that since the sequential section has the state assignment at each clock edge, so that "state" is forced to change, that triggers the @(*) sensitivity list so that it then calculates "next_state"?

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