Verilog - range handling with named values

Question

I have assigned names to numbers using:

`define ADD 0
`define SUB 1
`define LSF 2
`define RSF 3
`define AND 4
`define OR 5

I'd like to handle in a case block such that the code will apply for more than one option. In C this can be done using:

switch (x){

case ADD:
case SUB:
case LSF:
case RSF:
case AND:
case OR:
    printf ("Handling");
    break;
}

Is there a way to achieve that in Verilog? Thanks!

Marty · Accepted Answer · 2015-05-30 18:12:49Z

6

Yup, commas!

case (x)
ADD, SUB, LSF, RSF, AND, OR: begin
    $display("Handling multiple cases");
    // no need for breaks
end
MULT: begin
    $display("handle a single case");
end
default: begin
    $display("do something to do for all other cases");
end
endcase

answered May 30, 2015 at 18:12

Marty

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