Include a Verilog Header file using a Do file for Modelsim

Question

In a system-verilog file that I was given is an include for a Verilog Header file (.vh). When I manually run a simulation in Modelsim I usually go into the properties of the file ("Verilog & SystemVerilog" tab) and include the directory that holds the header file there. How would I go about making reference to it in a .do file that I am trying to create?

Unn · Accepted Answer · 2015-08-20 10:20:52Z

3

Assuming you have a file included with the `include macro; you should be able to use the +incdir+<path> argument to the compile command; where path is the path to the directory containing the .vh or .svh file(s).

answered Aug 20, 2015 at 10:20

Unn

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