FPGA implement memory mapped register

Question

i'm relatively new at fpga (vhdl) programming. So i have no clue about resource cost of different solutions to a problem... So i was wondering which approach makes most sense if i want to implement some memory mapped registers inside an fpga design. Should i design 1 address decoder that strobes al the registers on an address match or is it better to design each register with its own decoder (or at least each subcomponent like pwm generator which uses a couple of registers in my implementation).

Thanks in advance for the insights Regards Jan

Morten Zilmer · Accepted Answer · 2016-01-29 11:36:51Z

4

The critical resource is usually not gates (LUTs), but engineering time, and so the primary concern is to make the design easy to manage and modules easy to reuse.

For that reason alone, you should make a hierarchical address decode, where each module is responsible for partitioning and decode of the address space it has been allocated.

So in your case, the PWM generator should have separate address decoder for registers allocated in the address space given to the PWM module at the next higher level in the hierarchy.

To learn about resource usage you can install a FPGA synthesis tool and experiment with different approaches; that is a good exercise which will help you choose between different implementations.

answered Jan 29, 2016 at 11:36

Morten Zilmer

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Russell Over a year ago

This is the correct approach. You might see some older FPGA designs using the "centralized" bus approach, where all register decoding is done in one central module. This does not lend itself to portability or reusability. Creating a distributed register interface is significantly easier for reuse, it lends itself nicely to documentation, and resource utilization is lower.

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