Verilog issue with case/always statement

Question

I've coded this module for class using the example code given, but I'm getting errors when trying to compile - I think it may be due to the way I'm utilizing the inputs (Or just a syntax error), so I'm attempting to do it with arrays - Is my commented approach correct? Am I supposed to use concatenation?

module ledSwitch(LEDR, SW);
    input [9:0] SW; //switches and led
    output [0] LEDR;
 
    mux7to1 u0(
        .s0(SW[0]),//input switches to mux
        .s1(SW[1]),
        .s2(SW[2]),
        .s3(SW[3]),
        .s4(SW[4]),
        .s5(SW[5]),
        .s6(SW[6]),
        .s7(SW[7]),
        .s8(SW[8]),
        .s9(SW[9]),
        //.inputs([SW[0], [SW[1], [SW[2], [SW[3], [SW[4], [SW[5], [SW[6]])
        //.muxSelect([SW[7], [SW[8], [SW[9])
        .l(LEDR[0]) //input led output to mux
        );
endmodule

module mux7to1(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, l);
    input s0;
    input s1;
    input s2;
    input s3;
    input s4;
    input s5;
    input s6;
    input s7;
    input s8;
    input s9;
    //input inputs[6:0]
    //input muxSelect[2:0]

    output l;

    reg Out; //declare the output signal for the always block

    always@(*) //declare always block
    begin
        case ([s9, s8, s7])//muxSelect[2:0] //start case statement
            3'b000: Out = s0; //case 0, A
            3'b001: Out = s3; //case 1, D
            3'b010: Out = s1; //case 2, B
            3'b011: Out = s5 //case 3, F
            3'b100: Out = s0; //case 4, A
            3'b101: Out = s4; //case 5, E
            3'b110: Out = s2; //case 6, C
            3'b111: Out = s6; //case 7, G
            default: Out = 0; //Default        
        endcase
    end
    assign l = Out;
endmodule

Here's the error message:

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition

Info: Processing started: Tue Feb 2 14:53:06 2016

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab2_1 -c Lab2_1

Warning (20028): Parallel compilation is not licensed and has been disabled

Error (10170): Verilog HDL syntax error at Lab2_1.v(43) near text "["; expecting an operand

Error (10170): Verilog HDL syntax error at Lab2_1.v(45) near text "3"; expecting "end"

etc.

toolic · Accepted Answer · 2016-02-02 23:55:38Z

2

You need to use concatenation operator: case ({s9, s8, s7})

Also you have a few syntax errors like missing semicolons that you need to correct.

Finally in the ledSwitch module you need to define the output correctly.

edited Feb 2, 2016 at 23:55

toolic

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answered Feb 2, 2016 at 21:26

DBB

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