7-segment display with hex output

Question

I am trying to utilize a 7-segment display. I have written a module which I want to take 4 inputs and change the hex output. There seems to be an issue with unpacked/packed arrays. Any help is appreciated.

module hexDisplay (hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output hex [6:0];       
    reg out [6:0];
 
    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
      assign hex = out;
     end
endmodule

Errors:

Error (10773): Verilog HDL error at lab2pre.v(55): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions Error (10133): Verilog HDL Expression error at lab2pre.v(61): illegal part select of unpacked array "out"

Error (10133): Verilog HDL Expression error at lab2pre.v(62): illegal part select of unpacked array "out"

Error (10048): Verilog HDL error at lab2pre.v(64): values cannot be assigned directly to all or part of array "hex" - assignments must be made to individual elements only

Error (10137): Verilog HDL Procedural Assignment error at lab2pre.v(64): object "hex" on left-hand side of assignment must have a variable data type

Error (10044): Verilog HDL error at lab2pre.v(64): expression cannot reference entire array "out"

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 1 warning Error: Peak virtual memory: 959 megabytes Error: Processing ended: Tue Feb 2 17:33:35 2016 Error: Elapsed time: 00:00:15 Error: Total CPU time (on all processors): 00:00:46

Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 1 warning

Karan Shah · Accepted Answer · 2016-02-04 18:09:40Z

2 Errors :

You need to have "packed" array rather than an "unpacked" array for "out" & "hex" nets.

SystemVerilog supports both packed arrays and unpacked arrays of data. The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name.

bit [7:0] c1; // packed array of scalar bit types real u [7:0]; // unpacked array of real types

A packed array is a mechanism for subdividing a vector into subfields, which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits.

An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

So in the code, you require, out & hex to be used as a continuous bit vector, then it should be packed array, instead of unpacked array.

Refer to topic 7.4 of the Systemverilog LRM.
assign statement to hex, cannot be with in always block. Because an assign statement is used for modeling only combinational logic and it is executed continuously. So the assign statement is called 'continuous assignment statement' as there is no sensitive list.

So it can't be within always block, which is executed as per sensitivity list.

So your final working code is as below:

module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output [6:0] hex;       
    reg [6:0] out;

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
     end

    assign hex = out;
endmodule

toolic · Accepted Answer · 2023-08-19 09:32:00Z

1

Try something like this. Move the range specifiers ([6:0]) to the left of the signal names, and move the assign outside of the always block.

module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output [6:0] hex;
    reg [6:0] out;

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
     end
     assign hex = out;

endmodule

edited Aug 19, 2023 at 9:32

answered Feb 2, 2016 at 23:52

toolic

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Comments

Dixita Patel · Accepted Answer · 2016-02-05 12:21:58Z

-1

whatever variable in always block must be reg , here you assign hex in always which is by default wire so if you assign hex at out side of always u will get compile free code.

answered Feb 5, 2016 at 12:21

Dixita Patel

1

1 Comment

DAnsermino Over a year ago

I've since solved my issue, but I'm interested in what you're getting at as I want to learn more about verilog. As I understand a wire can only hold 1 value, but here when I declare hex I assign it 7 indices(not sure what the true term is). What does output [6:0] hex; really do? Also, am I not assigning hex outside of my always block? Could I just forget about my hex variable and do something like output reg [6:0] hex;?

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