Automatic Verilog code generation issue

Question

I am trying to make the generation of FSM state parametric or automatic. I tried many ways and seems there is no way to generate the code I need. Can someone help please?

The Code which I need to generate is part of FSM state machine, for the ST_DATA_CHECK state:

always @(posedge ui_clk_sync_rst or posedge ui_clk)
  begin
    if (rst) begin
      s_app_cmd           <= 3'b111;
      s_app_en            <= 1'b0;
end
end else begin
        case (ddr3_state)
          ST_INIT :
….
          ST_DATA_CHECK :   // This part of the code, needs to make parameteric
              if (~dwfifo_ef[0]) begin
                s_data_write_active[0] <= 1'b1 ;
              end else if (~dwfifo_ef[1]) begin
                s_data_write_active[1] <= 1'b1 ;
              end else if (~dwfifo_ef[2]) begin
                s_data_write_active[2] <= 1'b1 ;
              end else if (~d_rfifo_ef[0]) begin
                s_data_read_active[0] <= 1'b1 ;
              end else if (~d_rfifo_ef[1]) begin
                s_data_read_active[1] <= 1'b1 ;
              end
          ST_WRITE :
               …
endcase

Please notice that for example dwfifo_ef[0] and dwfifo_ef[1] bits can be 0 at the same time, so that’s why I need to use priority encoder here.

Any help/idea/suggestion is welcomed about how I can make the code parametric.

Thanks Hayk

dave_59 · Accepted Answer · 2016-03-25 06:41:49Z

1

You want a for loop with a break statement:

ST_DATA_CHECK :   
              for (int i=0;i<$bits(dwfifi_ef);i++)
              if (~dwfifo_ef[i]) begin
                s_data_write_active[i] <= 1'b1 ;
                break;
              end

answered Mar 25, 2016 at 6:41

dave_59

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2 Comments

haykp Over a year ago

Thanks Dave for answer However there are 2 items with your sollution 1) in my if statement there are 2 signals s_data_write_active and s_data_read_active 2) also I am not sure if for-break is synthesisable statement

Matthew Over a year ago

@haykp for loops are generably synthesisable. The loop parameters need to be static - it needs to be crystal clear what the maximum number of iterations of the loop will be.

Matthew · Accepted Answer · 2016-03-25 08:04:28Z

1

@dave_59 has just about solved your problem, but as you say "in my if statement there are 2 signals s_data_write_active and s_data_read_active", how about trying something like this?

ST_DATA_CHECK : 
              if (|dwfifo_ef == 1'b1)
                for (int i=0;i<$bits(dwfifi_ef);i++)
                  if (~dwfifo_ef[i]) begin
                    s_data_write_active[i] <= 1'b1 ;
                    break;
                  end 
              else 
                for (int i=0;i<$bits(d_rfifo);i++)
                  if (~d_rfifo[i]) begin
                    s_data_read_active[i] <= 1'b1 ;
                    break;
                end

(I have not tried to compile, simulate or synthsise this, hence my phrase something like.)

answered Mar 25, 2016 at 8:04

Matthew

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3 Comments

haykp Over a year ago

Thanks well this might work i.e. for simulation it can give good results however, how about synthesis and P&R? I will try to synthesise this, to see if for-break is synthesisable at all

Matthew Over a year ago

@haykp As I say, it ought to synthesise. Let us know how you get on.

haykp Over a year ago

Working! I could synthesize it by Synplify Thanks much for the help

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