Using reg output as input Verilog

Question

So, I'm working on a simple register that takes a synchronized input and, as soon as input is asserted, holds that state until reset is enabled.

My code should be pretty self explanatory. Is this checking-of-reg-output going to cause any problems?

    module walk_reg(
        input Walk_Sync,    //pedestrian set walk-request
        input WR_Reset,     //FSM reset, for during the walk service
        input clk,      //clock
        output reg WR   //output
        );


    always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

    endmodule // walk_reg

EDIT Changed name of variable, forgot to change it in code

Morgan · Accepted Answer · 2016-05-04 08:08:31Z

2

Not answer but too much for a comment.

always @(posedge (clk)) 
    begin
        if(WR_Reset)    //if reset enables, output goes to 0
            WR <= 1'b0;
        else if (WR)    //if WR is already on, keep it on
            WR <= WR;
        else 
            WR <= Walk_Sync;    //if reset is not enabled and WR isn't already one, assign output to Walk_Sync
    end

Is the same as:

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (!WR)    
    WR <= Walk_Sync;
end

Flip-flops will hold their value if no condition is met.

Even better suggestion from duskwuff:

always @(posedge clk) 
begin
  if (WR_Reset)    //if reset enables, output goes to 0
    WR <= 1'b0;
  else if (Walk_Sync)    
    WR <= 1'b1;
end

edited May 4, 2016 at 8:08

answered May 3, 2016 at 18:12

Morgan

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1 Comment

user149341 Over a year ago

Or alternatively, possibly a bit clearer: … else if (Walk_Sync) WR <= 1'b1.

Sourabh · Accepted Answer · 2016-05-05 04:04:27Z

0

on a side note, the WR_Reset will only reset the flop only when the clock is working. In most of the Flop designs, we use ASYNC reset edge detection then the reset detection based on clock.

always @(posedge (clk)) vs always @(posedge (clk) or posedge(WR_Reset))

Otherwise, no problem in using WR for conditional assignment.

answered May 5, 2016 at 4:04

Sourabh

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