Is it allowed to instantiate a module inside always_comb block in system verilog?

Question

Is it allowed to instantiate a module inside always_comb block in system verilog?

always_comb 
begin
   OR OR1 (.Y(A), .A(Z), 
end

if you really want to use conditional hardware, convert your module to task or function and call it conditionally. It increase your hardware resources but will meet your requirement. — Prakash Darji
– Prakash Darji, Commented May 17, 2016 at 8:54
Is there any particular reason your trying todo this rather than just instantiating it? — Morgan
– Morgan, Commented May 17, 2016 at 12:55

sharvil111 · Accepted Answer · 2016-05-17 08:24:22Z

First of all, your code is incomplete. Obviously, a two-input OR gate requires three connections.

In verilog, when you are instantiating a module, that means you are adding extra hardware to the board.

This hardware must be added before simulation starts(i.e. at compile time). Here, you can not add/remove hardware at each clock pulse.

Once instantiated, the module is executed/checked for each timestamp of simulation, till the end.

So to execute any module, just instantiate it, providing the required inputs to it (and add the always block in the sub-module itself, if necessary).

// Simply instantiate module
OR OR1 (.Y(A), .A(Z), .B(M));

Either way, you can add a combinational block to the current module itself:

// Directly use ORing
always_comb begin
  A = Z | M;
end

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