Instantiate Modules in Generate For Loop in Verilog

Question

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them.

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

a & b are declared as input arrays to the parent module and out is declared as a array of wires.

What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me:

Error (10644): Verilog HDL error at driver.v(63): this block requires a name

Line 63 is the for loop above. Any help is appreciated!

Can you show a,b,out declaration in status and current module? Seems like single instance is created 10 times. — sharvil111
– sharvil111, Commented Nov 24, 2015 at 17:30

vasilescur · Accepted Answer · 2019-01-30 15:49:38Z

23

You can apply label identifier to begin-end block with a colon after the begin (example: begin : label - end. This has always been an optional feature for generate blocks, though it is highly recommended. Quartus should not be giving an error.

It is an easy fix to satisfy Quartus-- add a label of any name you want:

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin : generate_block_identifier // <-- example block name
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

edited Jan 30, 2019 at 15:49

vasilescur

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answered Nov 24, 2015 at 17:26

Greg

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Comments

simap · Accepted Answer · 2019-11-13 18:56:38Z

8

I know this doesn't directly answer the question, but you can also declare several modules in this formation without using a generate block like so for 10 instances:

status whatever_status[9:0] (
  .clk(clk),
  .reset_n(reset_n),
  .a(a),
  .b(b),
  .out(out)
);

This is equivalent to the generate block above assuming that a, b, and out being passed are declared as [9:0]. This syntax will work as long as they're integer multiples of how they're declared in the module; they'll be spread evenly among each instance, otherwise synthesis will throw an error.

For example if a, b, and out are declared [19:0], then every 2 bits will be passed to each instance, and it is assumed they are declared as [1:0] within the module status.

edited Nov 13, 2019 at 18:56

simap

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answered Dec 17, 2016 at 20:10

Patrick Roberts

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2 Comments

Patrick Roberts Over a year ago

@simap thanks for the edit. I noticed the <= 10 in the question but failed to notice the initializer was i = 1 instead of i = 0 (as would be typical). That was what threw me off and wrote an answer talking about 11 instances.

artless-noise-bye-due2AI Jun 13 at 14:06

This (instantiation arrays) works for generate equivalents where indexes are 'i' only. Ie, the genvar. It does not work if the index is a computation. For instance, you may have i, i+5, i+10, etc. for a rerating filter with x5 up-sample, etc. Unless you are constrained to really old Verilog dialects (pre-2001), the generate syntax is more universal.

toolic · Accepted Answer · 2015-11-24 17:25:50Z

4

Give your block a name:

for (i=1; i<=10; i=i+1) begin: my_status

answered Nov 24, 2015 at 17:25

toolic

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