Specifying modport for interface inside an interface in SystemVerilog

Question

I have two interfaces with modports and another interface which combines these two interfaces as shown below:

interface my_interface1
 // Some signals
 modport tb_to_dut (
    // Signal directions specified
 )
endinterface

interface my_interface2
 // Some signals
 modport tb_to_dut (
    // Signal directions specified
 )
endinterface

interface my_combined_interface
  my_interface1 inf1
  my_interface2 inf2
endinterface

I wanted to specify a modport for the combined interface which in turn calls/uses the modport of the individual interfaces. The idea is as shown below.

interface my_combined_interface
  my_interface1 inf1
  my_interface2 inf2

  modport tb_to_dut (
     inf1.tb_to_dut,
     inf2.tb_to_dut
  )
endinterface

This currently results in a syntax error. Is there a way by which I can specify the modport in the combined interface such that it percolates down to the individual interfaces?

dave_59 · Accepted Answer · 2016-05-25 20:45:25Z

3

Unfortunately, SystemVerilog interfaces lack compositional qualities and there is no way to specify an interface in pieces. The only way to do this today is to flatten out the combined interface by bringing the lower level interface signals up to the top level. And I would avoid using modports altogether for the testbench.

answered May 25, 2016 at 20:45

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Specifying modport for interface inside an interface in SystemVerilog

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related