Verilog "In, out, or inout does not appear in port list"

Question

I can't understand what this error means. I want to make a simple calculator with memory, however this error jumped out and I cant get what the

** Error: C:\Users\Kainy\Desktop\LOGIC\calculator\cal.v(14): In, out, or inout does not appear in port list: f1. ** Error: C:\Users\Kainy\Desktop\LOGIC\calculator\cal.v(15): In, out, or inout does not appear in port list: f2.

means. Seems my f1, f2 have some invalid things, how can I fix it?

module cal( a,b,c,op,clk,reset,en,r_w);     
input [3:0] a;
input [3:0] b; 
input [7:0] c; 
input [2:0] op; 
input clk;
input reset;
input en;
input r_w;



output reg [7:0] f1;
output reg [7:0] f2; 


wire [7:0] f3;




always@(a or b or op) begin
case(op)
3'b000: begin
 f1 = a;
 f3 = f1;
end

3'b001: begin
 f1 = b;
 f3 = f1;
end


3'b010: begin 
 f1 = a+b;
 f3 = f1;
end

3'b011: begin
 f1 = a - b;
 f3 = f1;
end

3'b100: begin
 f1 = a * b;
 f3 = f1;
end

3'b101: begin
 f1 = b+a;
 f3 = f1;
end

3'b110: begin
 f1 = b-a;
 f3 = f1;
end

3'b111: begin
 f1 = 0;
 f3 = 0;
end
endcase
end

mem32 mem(clk,reset,en,r_w,c,f3,f2);

endmodule

Hi, welcome to Stack overflow! May I suggest two improvements to your question that will greatly increase your chances of a powerful answer? 1: Always include a clear question & problem description in your post. It's probably ok to repeat a rephrased version at the end of your post if you have a long block of text, as well. 2: Please include a section where you describe in detail what it is that you have tried. — Kzqai
– Kzqai, Commented Aug 30, 2016 at 16:11

Matthew · Accepted Answer · 2018-06-22 07:53:09Z

5

You have specified f1 and f2 as being outputs, but have not specified them in the port list: in other words, f1 and f2 do not appear on this line: module cal( a,b,c,op,clk,reset,en,r_w);.

Incidentally, you are using a very old-fashioned style. In 2001 this style (the "ANSI style") was introduced:

module cal(      
  input [3:0] a,
  input [3:0] b, 
  input [7:0] c, 
  input [2:0] op, 
  input clk,
  input reset,
  input en,
  input r_w,
  output reg [7:0] f1,
  output reg [7:0] f2
);

Had you used this ANSI style, your error would never had occurred.

I always recommend ANSI style for all new code to the people I teach. I teach this old-fashioned style, but mention that I am only doing so so that they can understand legacy code.

edited Jun 22, 2018 at 7:53

answered Aug 30, 2016 at 16:04

Matthew

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3 Comments

Kainy Yang Over a year ago

And there's another error, Illegal reference to net "f3". Can you teach me why this happens? Thank you.

Matthew Over a year ago

@KainyYang Yes, because you are assigning to a wire from an always block. That is not allowed. f3 needs to be a reg.

teadotjay Over a year ago

@MatthewTaylor Another reason to teach the original style is that synthesis tools will output netlists in this format and downstream tools will fail to read netlists in the ANSI style.

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