Illegal output or inout port connection for port

Question

I am unsure as to why I am receiving the above stated error when attempting to run a simulation, and am also unsure how to fix it. Please advise.

I've attached my source code below, along with the testbench module and the errors I received when trying to run the simulation.

module test1();
   reg O, P, W;  
   wire LowRate, StandardRate, PeakRate;   
   outputs LowRate,StandardRate,PeakRate


   CircuitStructure 
testboi(LowRate,StandardRate,PeakRate,O,P,W);

   initial
   begin
O=0; P=0; W=0;
#10 O=0; P=0; W=0;
#10 O=0; P=0; W=1;
#10 O=0; P=1; W=0;
#10 O=0; P=1; W=1;
#10 O=1; P=0; W=0;
#10 O=1; P=0; W=1;
#10 O=1; P=1; W=0;
#10 O=1; P=1; W=1;

#10
$finish();
end
endmodule


module CircuitStructure(O, P, W, LowRate, 
   StandardRate, PeakRate);

   input O, P, W;  
   output LowRate, StandardRate, PeakRate;

   not
    UA1(NotP,P),
    UA2(NotO,O),
    UA3(NotW,W);

   nand
    UB1(Nand1,NotP,NotO),
    UB2(Nand2,NotW,P),
    UB3(PeakRate,Nand1,Nand2);

   and
    UC1(StandardRate,P,W);

   buf
    UD1(LowRate,O);
endmodule

Simulation Errors:

Loading work.test1
# Loading work.CircuitStructure
# ** Error (suppressible): (vsim-3053) 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v(10): Illegal         
output or inout port connection for port 'LowRate'.
#    Time: 0 ns  Iteration: 0  Instance: /test1/testboi File: 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v
# ** Error (suppressible): (vsim-3053) 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v(10): Illegal 
output or inout port connection for port 'StandardRate'.
#    Time: 0 ns  Iteration: 0  Instance: /test1/testboi File: 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v
# ** Error (suppressible): (vsim-3053) 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v(10): Illegal 
output or inout port connection for port 'PeakRate'.
#    Time: 0 ns  Iteration: 0  Instance: /test1/testboi File: 
C:/Modeltech_pe_edu_10.4a/ECE171_Project1/TestBench - Copy.v
# Error loading design

Qiu · Accepted Answer · 2018-11-05 08:59:04Z

You have defined your module as:

module CircuitStructure(O, P, W, LowRate, StandardRate, PeakRate);

However, defining your unit test, you use different signals order:

testboi(LowRate,StandardRate,PeakRate,O,P,W);

That's why compiler assumes you want to assing LowRate signal to O input, StandardRate to P input, etc. IEEE Standard 1800-2017 (ch. 23.3.2) define following ways to connect modules instances:

Positional connections by port order,
Named port connections using fully explicit connections,
Named port connections using implicit connections (SystemVerilog),
Named port connections using a wildcard port name (SystemVerilog).

Using the first one, you need to change your signals order:

testboi(O,P,W,LowRate,StandardRate,PeakRate);

Using the second one, you need to explicitly "tell" compiler which signals are assigned to particular ports:

testboi(.LowRate(LowRate),.StandardRate(StandardRate),.PeakRate(PeakRate),.O(O),.P(P),.W(W));

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