Systemverilog bit-shift difference between {<<{signal}} and {signal<<1}?

Question

I have the following piece of code which the Vivado simulator doesn't seem to support (results in ERROR: [XSIM 43-3209] - Unsupported Construct):

assign b = {<<{a}};

Wondering if I can just change this code to the following:

assign b = a<<1;

Could someone please confirm that the 2 lines above are identical? Note that both a and b are 8 bit wide. Thanks!

dave_59 · Accepted Answer · 2016-09-01 06:10:12Z

4

No they are not the same. {<<{a}} is a bit reversal. Assuming a was declared with the range [7:0], you would need to write

assign b = {a[0],a[1],a[2],a[3],a[4],a[5],a[6],a[7]};

answered Sep 1, 2016 at 6:10

dave_59

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