I am trying to instantiate a verilog module multiple times with different instance name such that it depend on a Macro definition. It is something like this
`define CHAN_NO 0
mymodule #(.chan_no(`CHAN_NO)) inst<CHAN_NO> (
.Addr (ADDR_A )
,.Data (DATA_A )
,.Clk (CLK )
);
of course this is a simplified example because instantiation and macro come from different files.
Is this possible , if yes what is right way of doing such instantiation.
Of course it is possible. You should use generate block:
genvar i;
generate
for (i = 0; i < `CHAN_NO; i=i+1)
begin : mymodule_instance
mymodule #(.chan_no(i)) mymodule_inst (
.Addr (ADDR_A )
,.Data (DATA_A )
,.Clk (CLK )
);
end
endgenerate
After elaboration tree should look like this (for example CHAN_NO = 3):
mymodule_instance[0]
mymodule_inst
mymodule_instance[1]
mymodule_inst
mymodule_instance[2]
mymodule_inst
Edit: If you want to have an instance name that is dependent on macro then you can do it like this:
`define INSTANCE_NUM 0
`define INSTANCE_NAME(x) instance_name``x``
mymodule #(.chan_no(`INSTANCE_NUM)) `INSTANCE_NAME(`INSTANCE_NUM) (
.Addr (ADDR_A )
,.Data (DATA_A )
,.Clk (CLK )
);
