Quote macro literal string argument inside string

Question

I have the following macro:

`define check(CONDITION) \
  begin \
    if (!(CONDITION)) \
      $display("'%s' failed.", `"CONDITION`"); \
  end

And the following expansions:

module test;
  initial begin
    `check(0)
    `check(1 == 0)
  end
endmodule

They print the following:

'0' failed.
'1 == 0' failed.

If I have a condition over strings, though, then the macro expansion won't work properly. Concretely, adding the following line leads to a compile error:

`check("foo" == "bar")

What I would like, though, is to have the following printed:

'"foo" == "bar"' failed.

Is there a way to write the macro body that would allow this? I would like to avoid solutions where I have two macros, one where strings aren't allowed inside the condition and one explicitly for strings.

dave_59 · Accepted Answer · 2016-12-15 16:36:22Z

1

You can't do this with just one macro in SystemVerilog. It would take something like the qq() operator in PERL for this to work.

answered Dec 15, 2016 at 16:36

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

3 Comments

Tudor Timi Over a year ago

I take it it's not possible to build such an operator using the language itself. Would one idea be using VPI to parse a system function's argument and return it as a string? I saw that there are some pretty powerful functions for introspection, including source code introspection.

dave_59 Over a year ago

Doing this with the VPI would be quite complex. And that's assuming tools have implemented all the VPI routines needed.

Tudor Timi Over a year ago

For sure, but it might make for a nice exercise. Hopefully my tool wont disappoint either.

Collectives™ on Stack Overflow

Quote macro literal string argument inside string

1 Answer 1

3 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

3 Comments

Your Answer

Sign up or log in

Post as a guest

Related