How to convert a string to a variable name?

Question

I would like to have a construct like below to declare variable names based on a string queue. The below doesn't compile. So I would like to know if a similar approach is possible in Systemverilog.

Below is a simplified version of what I want to actually implement.

`define declare_int(NAME) int ``NAME`` = 1;

string str_q[$] = {"a", "b", "c"};
foreach (str_q[i]) begin
   `declare_int(str_q[i])
end

NOTE: I am aware that `declare_int(a) will translate to int a = 1;. But as shown in the example above, I need a foreach loop to call this macro multiple times and so the input of the macro has to be some datatype, like a string in this case. The purpose is to auto-declare stuff as the queue changes with time.

In other words, how can I define the `declare_int macro so that `declare_int("a") translates to int a = 1;?

Unn · Accepted Answer · 2014-10-07 16:03:54Z

2

As Verilog is not interpreted but compiled in simulation, I doubt theres any way to dynamically declare variables at runtime. However, there are work arounds that achieve a similar effect.

I think the closest thing you could get is an associative array with the keys as your names (a, b, c) and your values for the values. For example, instead of your code, you'd have:

int vars[string];
string str_q[$] = {"a", "b", "c"};
foreach (str_q[i]) begin
  vars[str_q[i]] = 1;
end
...
// To use the variable, just do:
vars["a"];

For more on associative arrays: http://www.asic-world.com/systemverilog/data_types13.html

answered Oct 7, 2014 at 16:03

Unn

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