When exactly to use logic data type and when bit data type in system verilog?

Question

I know that logic is a 4-state and bit is 2 state, using bit will make to lose testing of x and z. But when exactly bit and when logic?

Possible duplicate of Difference of SystemVerilog data types (reg, logic, bits) — rodridevops
– rodridevops, Commented Dec 28, 2016 at 4:37

Arun D'souza · Accepted Answer · 2016-12-28 20:01:51Z

0

This paper should cover your questions:

TLDR; bit is better for performance (only 2 states to model), but hides X-propagation issues.

answered Dec 28, 2016 at 20:01

Arun D'souza

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