Verilog: Implementation Using Primitive Modules vs. Bit-wise Operators

Question

The textbook I'm reading implements 1-bit adders using built-in primitive modules:

module yAdder1(z, cout, a, b, cin);
     output[0:0] z, cout;
     input[0:0] a, b, cin;
     wire[0:0] tmp, outL, outR;

     xor left_xor(tmp, a, b);
     xor right_xor(z, cin, tmp);
     and left_and(outL, a, b);
     and right_and(outR, tmp, cin);
     or my_or(cout, outR, outL);
endmodule

But why not use bit-wise operators? Seems simpler.

module yAdder1(z, cout, a, b, cin);
     output[0:0] z, cout;
     input[0:0] a, b, cin;

     assign z = (a ^ b) ^ cin;
     assign cout = (a & b) | ((a ^ b) & cin);
endmodule

Unless bit-wise operators implicitly use primitive modules?

Serge · Accepted Answer · 2017-07-01 00:18:21Z

1

builtin primitives are a convenient way to express gates in gate-level models. Usually they are generated by other tools. Other than that there is no much reason for using them in the regular verilog.

There are probably few of them which you can run across, mostly a variety of tristate buffers which could be used for driving buses. But all others are not that used as much.

And no they are not use implicitly in simulation.

answered Jul 1, 2017 at 0:18

Serge

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1 Comment

NoName Over a year ago

Ah I see, Gate (Structural) Level abstraction vs. Functional and Algorithmic Level (Behavioral) abstraction. Each with their own pros and cons.

user8238697 · Accepted Answer · 2017-07-01 07:50:32Z

0

It's just a different style of writing verilog. The former is in a structural format, and the latter is more towards behavioral/functional format.

Adding to @Serge's point, If you try to synthesize each of them separaetely, you'll see a very similar (may be exactly same) netlist. Writing your code in a structural manner will ease the effort on the synthesis tool to map the RTL to existing primitives (in the characterized library)- the downside being the difficulty to understand the functionality looking at a structual code.

answered Jul 1, 2017 at 7:50

user8238697

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