iverilog syntax for include?

Question

I'm trying to include a Verilog file (alu.v) in my main file (cpu.v). Both files are in the same directory.

'include "alu.v"

 module cpu();
 ...
 ...
 endmodule

When I try to compile it, I get the following error.

cpu.v:1 syntax error
I give up

I don't see how the include statement is wrong. I'm sure my syntax is correct like shown here.

Krouitch · Accepted Answer · 2017-02-09 15:12:54Z

4

Don't be so sure! Proof you mess with something, it does not work.

The preprocessor directives in Verilog begin with a back-tick (`) not an apostrophe (').

Try:

`include "alu.v"

Instead of:

'include "alu.v"

answered Feb 9, 2017 at 15:12

Krouitch

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