I am implementing a 4 bit counter using a D flip flop. For that, I have first written the code of D flip-flop then converted it to T flip-flop and then used it to make a counter.
The problem I am facing is that only first instance of T_flipflop "T0" is working while other bits are on unknown state.
The output of the code!!
# 0 T = 1 , Clock=0 , q= x , q= xxxx , Reset= 1
# 10 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 1
# 15 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 0
# 20 T = 1 , Clock=0 , q= X , q= xxx0 , Reset= 0
# 30 T = 1 , Clock=1 , q= X , q= xxx1 , Reset= 0
# 40 T = 1 , Clock=0 , q= X , q= xxx1 , Reset= 0
# 50 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 0
# 60 T = 1 , Clock=0 , q= X , q= xxx0 , Reset= 0
# 70 T = 1 , Clock=1 , q= X , q= xxx1 , Reset= 0
# 80 T = 1 , Clock=0 , q= X , q= xxx1 , Reset= 0
# 90 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 0
# 100 T = 1 , Clock=0 , q= X , q= xxx0 , Reset= 0
# 110 T = 1 , Clock=1 , q= X , q= xxx1 , Reset= 0
# 120 T = 1 , Clock=0 , q= X , q= xxx1 , Reset= 0
# 130 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 0
# 140 T = 1 , Clock=0 , q= X , q= xxx0 , Reset= 0
# 150 T = 1 , Clock=1 , q= X , q= xxx1 , Reset= 0
# 160 T = 1 , Clock=0 , q= X , q= xxx1 , Reset= 0
# 170 T = 1 , Clock=1 , q= X , q= xxx0 , Reset= 0
# 180 T = 1 , Clock=0 , q= X , q= xxx0 , Reset= 0
# 190 T = 1 , Clock=1 , q= X , q= xxx1 , Reset= 0
# 200 T = 1 , Clock=0 , q= X , q= xxx1 , Reset= 0
I have figured out a problem that my T flip flop is not working as expected. If I remove the input T from the T_flipflop module and assign the Q_bar to D, it work properly. How can i correct the T flip-flop without removing the input T_flipflop module.
module D_flipflop (Q, Q_bar ,D, clk,reset);
output reg Q;
output Q_bar;
input clk, reset ,D;
assign Q_bar=~Q;
always @(posedge clk)
begin
if(reset) //Active high reset
Q<=1'b0;
else
Q<=D;
end
endmodule
module T_flipflop (output Q, Q_bar , input T, clk,reset);
wire w;
assign w=T^Q;
D_flipflop D1(.Q(Q), .Q_bar(Q_bar) ,.D(w), .clk(clk),.reset(reset));
endmodule
module ripple_carry_counter(Q,T,Clk,reset);
output [3:0]Q ;
input Clk,reset,T;
T_flipflop T0(.Q(Q[0]), .Q_bar() ,.T(T), .clk(Clk),.reset(reset));
T_flipflop T1(.Q(Q[1]), .Q_bar() ,.T(T), .clk(Q[0]),.reset(reset));
T_flipflop T2(.Q(Q[2]), .Q_bar() ,.T(T), .clk(Q[1]),.reset(reset));
T_flipflop T3(.Q(Q[3]), .Q_bar() ,.T(T), .clk(Q[2]),.reset(reset));
endmodule
module exp_masood_bench_ripple_carry_counter;
reg clk,reset,T;
wire [3:0]q;
ripple_carry_counter MS(q,T,clk,reset);
initial
$monitor($time , " T = %b , Clock=%b , q= %d , q= %b , Reset= %b ",T,clk,q,q,reset);
initial
begin
clk=1'b0;
T=1'b1;
reset=1'b1;
#15 reset=1'b0;
#400 $finish;
end
always #10 clk=~clk;
endmodule
