VHDL: error when using "With Select When" Statement

Question

I'm learning VHDL using Altera Max V and Quartus to do some examples and I have a trouble when using "With Select when" statement. I have a simple 2-4 decoder as followed:

library ieee;
use ieee.std_logic_1164.all;

entity lesson9 is
    port(
        x: in std_logic_vector(1 downto 0);
        en: in std_logic;
        y: out std_logic_vector(3 downto 0)
    );
end lesson9;

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    decoder2to4: process(x)
    begin
        with x select
            outputBuff <= "0001" when "00",
                          "0010" when "01",
                          "0100" when "10",
                          "1000" when "11";
    end process decoder2to4;

    y <= outputBuff;
end rtl;

And I got the error message:

near text "with"; expecting "end", or "(", or an identifer ("with" is a reserved keyword), pr a sequential statement

I tried to check my code but couldn't find the problem ?

Which version of Quartus you are using? With-select it VHDL-2008 construct and not supported by older tool version. Also, make sure to enable VHDL-2008 for the file if using more recent Quartus version. — FritzDC
– FritzDC, Commented May 3, 2017 at 7:22
with ... select is not a VHDL-2008 construct, but it's new to allow with ... select within sequential code (e.g. a process). You need to either remove the process to make with ... select concurrent or enable compilation with 2008 features if your tool supports these. — Paebbels
– Paebbels, Commented May 3, 2017 at 12:49

Juergen · Accepted Answer · 2017-05-03 06:26:30Z

3

The with ... select statement is a concurrent signal assignment statement used outside of a process:

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    with x select
        outputBuff <= "0001" when "00",
                      "0010" when "01",
                      "0100" when "10",
                      "1000" when "11";

    y <= outputBuff when en='1' else (others=>'0');
end rtl;

I have also added the en signal in the output assignment statement.

Note: I did not simulate that code snippet.

answered May 3, 2017 at 6:26

Juergen

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5 Comments

user1155120 Over a year ago

There's also a sequential selected signal assignment statement in VHDL 2008. See IEEE Std 1076-2008 10.5 Signal assignment statement and 10.5.4 Selected signal assignments. Unfortunately not a feature supported by Quartus® Prime for synthesis.

Matthew Over a year ago

Why have you added the en signal in the output statement? There's nothing in the question to suggest that was necessary.

Juergen Over a year ago

Well, there is an en input port on the port list and it's quite easy to guess what it is intended for. It is certainly not a bug to declare input ports which are not used in the architecture, but synthesis/linting tools might complain about it. So I recommend to either use the port or remove it from the port list.

Roman Over a year ago

@Juergen if don't use a signal which declared, the signal will be optimized (i.e. removed) in synthesis process without any complains.

BL_ Over a year ago

Thanks @Juergen. I'll test it.

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