VHDL when-else error

Question

I'm new in VHDL and have simple errors. I'm trying to create MUX using when else construction. Errors are two types:

Error (10500): VHDL syntax error at lab13.vhd(21) near text "when"; expecting ";"

Error (10500): VHDL syntax error at lab13.vhd(21) near text "else"; expecting ":=", or "<="

And these errors are for every string with when else.

And here is the code:

entity lab13 is
port (SW : in  STD_LOGIC_VECTOR (17 downto 0);
LEDG : out STD_LOGIC_VECTOR (2 downto 0);
LEDR : out STD_LOGIC_VECTOR (17 downto 0));
end lab13;



architecture logicFunc of lab13 is
begin  
    process
variable a, b, c : STD_LOGIC_VECTOR (2 downto 0) :=0;
begin
    a(0) := SW(0) when (SW(15) = '0') else SW(3);
    b(0) := SW(6) when (SW(15) = '0') else SW(9);
    c(0) := a(0) when (SW(16) = '0') else b(0);
    LEDG(0) <= c(0) when (SW(17) = '0') else SW(12);

    a(1) := SW(1) when (SW(15) = '0') else SW(4);
    b(1) := SW(7) when (SW(15) = '0') else SW(10);
    c(1) := a(1) when (SW(16) = '0') else b(1);
    LEDG(1) <= c(1) when (SW(17) = '0') else SW(13);

    a(2) := SW(2) when (SW(15) = '0') else SW(5);
    b(2) := SW(8) when (SW(15) = '0') else SW(11);
    c(2) := a(2) when (SW(16) = '0') else b(2);
    LEDG(2) <= c(2) when (SW(17) = '0') else SW(14);
end process;
   LEDR <= SW;
end logicFunc;

So, how to solve these problems?

Hm, I'm not so familiar with that, but I think the problem is that you need to look in the synthesis or project options and set the VHDL mode to VHDL-2008 or VHDL-200x. See if you can find something like that. — scary_jeff
– scary_jeff, Commented Jun 13, 2016 at 9:48
You're trying to use a sequential conditional assignment statements (in a process) which appear to not be supported in the particular version of Quartus II. — user1155120
– user1155120, Commented Jun 13, 2016 at 9:57

Morten Zilmer · Accepted Answer · 2016-06-13 10:16:45Z

2

The when in sequential statement for conditional variable or signal assignment was introduced in VHDL-2008, which is not fully supported in Altera Quartus.

The implementation can instead be made with signals, and no process, like:

architecture logicFunc of lab13 is
  signal a, b, c : STD_LOGIC_VECTOR (2 downto 0);
begin

  a(0) <= SW(0) when (SW(15) = '0') else SW(3);
  b(0) <= SW(6) when (SW(15) = '0') else SW(9);
  c(0) <= a(0) when (SW(16) = '0') else b(0);
  LEDG(0) <= c(0) when (SW(17) = '0') else SW(12);

  a(1) <= SW(1) when (SW(15) = '0') else SW(4);
  b(1) <= SW(7) when (SW(15) = '0') else SW(10);
  c(1) <= a(1) when (SW(16) = '0') else b(1);
  LEDG(1) <= c(1) when (SW(17) = '0') else SW(13);

  a(2) <= SW(2) when (SW(15) = '0') else SW(5);
  b(2) <= SW(8) when (SW(15) = '0') else SW(11);
  c(2) <= a(2) when (SW(16) = '0') else b(2);
  LEDG(2) <= c(2) when (SW(17) = '0') else SW(14);

  LEDR <= SW;

end architecture;

The initialization value of a, b, and c is not required, and otherwise it must be made using:

variable a, b, c : std_logic_vector (2 downto 0) := (others => '0');

If something like when is handy before VHDL-2008, then a tern function can be written as:

function tern(cond : boolean; res_true, res_false : std_logic) return std_logic is
begin
  if cond then
    return res_true;
  else
    return res_false;
  end if;
end function;

And then used as:

a(0) := tern(SW(15) = '0', SW(0), SW(3));

edited Jun 13, 2016 at 10:16

answered Jun 13, 2016 at 9:57

Morten Zilmer

15.9k4 gold badges35 silver badges52 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

user1155120 Over a year ago

Or you could use one process and switch to if statements instead of conditional assignment statements. The idea that reducing the number processes from the number of assignments to one would simulate faster. Concurrent assignments imply separate processes.

user7427901 · Accepted Answer · 2019-10-30 17:18:38Z

The 'WHEN' keyword has 2 contexts within VHDL and are both applicable from VHDL 1993 onwards: 1. it is used as part of a 'CASE' statement within a process/procedure:

CASE xyz IS
  WHEN val1 =>  some sequential statements;
  WHEN val2 =>  some sequential statements;
  WHEN OTHERS => NULL;
END CASE;

By replacing the code between the BEGIN/END of you process with this will yeild the correct result whether you are using variables or signals.

it can used as a 'WHEN-ELSE' concurrent statement (not in a process/procedure):

result <= val1 WHEN some conditions are true ELSE val2 WHEN some other conditions are true ELSE (OTHERS => '0');

This will also return the required result but as not within a process/procedure will require the 'result' to be either a signal or a shared variable.

Collectives™ on Stack Overflow

VHDL when-else error

2 Answers 2

1 Comment

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

1 Comment

Comments

Your Answer

Sign up or log in

Post as a guest

Related