VHDL syntax error using when

Question

I have the following code:

DATA_LCD <= DATA_ROM when SW(1)='0' or char_code<97 or char_code>122 else
                 std_logic_vector(char_code-32); -- no modification in this code
                     DATA_ROM when SW(2)='0' else
                     std_logic_vector(char_code+1);

But when i try to compile it i get following errors:

Error (10500): VHDL syntax error at LCD_FSM.vhd(57) near text "="; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at LCD_FSM.vhd(57) near text "when"; expecting "(", or "'", or "."

How can I fix it?

It could be good to have more information, especially on the signal definition. But basically the second DATA_ROM just comes from nowhere, I don't get what you're trying to do there. — A. Kieffer
– A. Kieffer, Commented Jan 4, 2017 at 12:55
No more information needed. The third line is the start of a new (malformed) statement. (There was probably supposed to be another "when" clause on the second line) — user1818839
– user1818839, Commented Jan 4, 2017 at 12:56
Rows 3 and 4 just look like a (combinational) expression. Should it be driving something? — Yann Vernier
– Yann Vernier, Commented Jan 4, 2017 at 13:14
So what does SW(1) and SW(2) signify? The first condition expression appears to relate to an HD44780U type LCD controller (2 or 4 line LCD display). Fixing it requires understanding what it's supposed to do - you have two else condition values shown. — user1155120
– user1155120, Commented Jan 4, 2017 at 20:18

ARude · Accepted Answer · 2018-05-24 15:34:46Z

0

Brian is right, line 3 is a new (malformed) statement. You forgot to put another DATA_LCD <= at the beginning of it.

DATA_LCD <= DATA_ROM when SW(2)='0' else std_logic_vector(char_code+1);

edited May 24, 2018 at 15:34

answered Jan 4, 2017 at 18:08

ARude

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1 Comment

JHBonarius Over a year ago

I don't get your edit. The code you added does not match the OP question. Furthermore, this question is 16 months old!

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