I have a couple of errors in my verilog code that pop up when I compile. I believe they are all related. But I can't figure out what the error is. Any help will be greatly appreciated.
The errors are: Two for the input
vlog_a: Error 31004 Syntax error near `input' found
blog_a: Error 31004 Syntax error near 'output' found
module threeBitComparator;
input A2,A1,A0;
input B2,B1,B0;
output E,GE; //E-Equal, GE-Greater than or Equal to
wire X1,X2,X3; //xnor gate
wire Y1,Y2,Y3,Y4,Y5,Y6; // and & or gates
xnor
G1a(X1,A2,B2),
G1b(X2,A1,B1),
G1c(X3,A0,B0);
and
G2a(Y1,A2,~B2),
G2b(Y2,A1,~B1),
G2c(Y3,A0,~B0),
G2d(Y4,X1,Y2),
G2e(Y5,X1,X2,Y3),
G2f(E,X1,X2,X3);
or
G3a(Y6,Y1,Y4,Y5),
G3b(GE,Y6,E);
endmodule