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So, I have a theoretical question about the Chisel code transformation.

I already know that the Chisel code is compiled to Java bytecodes, it then runs in the JVM and it emits equivalent Verilog and C++ source codes (for older versions of Chisel).

But I'm having a lot of trouble in understanding that process. For instance, in the Chisel source code, I can see that there is a Reg class, for example, that creates a definition of a register. I can then import and use this class in the design of the hardware. But I cannot understand where the separation between the description of the Reg class itself and the actual usage of it lies. It's so confusing.

For example, suppose I'm developing a project that USES a Reg object, where there's a source code called whatever.scala, and inside this source code there are Reg objects. As I understand it, the description of the register itself (the Reg.scala) and the source code that uses it (whatever.scala) are all compiled at the same time, and that's precisely the point a cannot get.

To make it short, in my point of view, there is a separation between describing a library, and actually using this library after it was built. You must first compile the library, then you import it into your project and use it. But in Chisel, these two steps seem to happen at the same time.

Is there any intermediate process between the JVM code emission and the creation of the Chisel AST?

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Chisel is a high level highly parameterized embedded DSL for generating hardware design. A chisel program typically consists of several steps:

  • A chisel3 program first constructs an internal representations of an idealized circuit as an abstact syntax tree (AST). At the end of generation, the AST is serialized in to FIRRTL (an intermediate representation) representation. See: chisel3
  • The firrtl transformation engine process the high level FIRRTL produced with some number of transformation passes. These passes can optimize the code, do width inferences, and finally emit verilog or low firrtl. See: firrtl
  • Typically during development the circuit is then unit tested. There are two simple ways to do this.
    • The verilog emitted can be converted into an executable simulation via verilator and a c++ compiler. The simulation can be executed with a test harness that validates the circuit. See: chisel-testers
    • Or, the emitted firrtl can be simulated using the firrtl-interpreter a lightweight scala program, capable of running the same unit tests used with the chisel-testers. See: firrtl-interpreter

These steps can be run together, using chisel-tester can execute all the above steps automatically. Or done individually, each step can produce output files for the user to add custom integration or to target the verilog for FPGA or a chip tape-out.

The JVM is simply the execution environment used to run scala programs and is not necessary to understand or interact with in order to build circuits using Chisel.

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I understand your point. But there's still something confusing me, I'll give you an example: suppose that, in a hardware description that uses Chisel, there is a declaration of a register object, let's say, output_register=Reg(...). As a back end, there'll be a C++ or Verilog register that has roughly the same variable name. So, it's like Chisel can inspect its own variable names when it's transformed from Chisel to the other language, it seems like reflection. How does Chisel know it's own variable names when it's transformed?
Chisel does use reflection. When a module is created, at run time, the variables are inspected and ones who reference instances of chisel types. the names are derived from the variables names, scoped by the module hierarchy.
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To address the Chisel vs. your project question:

Chisel is a Scala library that is compiled to JVM bytecode. A project that uses Chisel is a Scala program that links against Chisel. This project is also compiled to JVM bytecode, but includes calls to the separately compiled Chisel library*. This project using Chisel is then executed, running on the JVM. The execution of this program constructs a hardware AST that is ultimately emitted as Verilog.

* Many projects (like rocket-chip) do include the Chisel source code as a subproject. Chisel is usually compiled first and then linked against. However, it should make no difference if it were compiled all at once--it's just Scala code that other Scala code invokes.

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