Generating Verilog code after BlackBoxing in Chisel3

Question

I am trying BlackBox feature in Chisel3. Every time I try to generate Verilog code of Chisel I got an error.

I followed the right steps, writing the class, class driver and build.sbt.

I am not sure where the problem is

This is my Chisel Code

import chisel3._
import chisel3.util._
import chisel3.experimental._

class BlackBoxRealAdd extends BlackBox with HasBlackBoxInline {
  val io = IO(new Bundle() {
    val in1 = Input(UInt(64.W))
    val in2 = Input(UInt(64.W))
    val out = Output(UInt(64.W))
  })
  setInline("BlackBoxRealAdd.v",
    s"""
      |module BlackBoxRealAdd(
      |    input  [15:0] in1,
      |    input  [15:0] in2,
      |    output [15:0] out
      |);
      |always @* begin
      |  out <= (in1) + (in2));
      |end
      |endmodule
    """.stripMargin)
}


object BlackBoxRealAddDriver extends App {
  chisel3.Driver.execute(args, () => new BlackBoxRealAdd)
}

scalaVersion := "2.11.12"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.1.+"

Alaa Salman · Accepted Answer · 2019-04-14 21:41:48Z

2

I have figured it out. The blackboxed module shouldn't be the top one.

answered Apr 14, 2019 at 21:41

Alaa Salman

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2 Comments

Jack Koenig Over a year ago

Glad you were able to figure it out!

Alaa Salman Over a year ago

It took time, Thank you ;)

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