Should Chisel generate verilog testbench logic?

Question

I have the following test code and call chiseMain with --genHarness. Verilog is generated for the harness but it contains none of the logic from the Tester class. Any thoughts on why I'm not getting the logic I expect? I am using Chisel 2.10.

Code:

class TestMultiPortedMem(c: MultiPortedMem) extends Tester(c) {
  var i = 0

  // Write address as data                                                                                    
  for (p <- c.io.wports) {
    poke(p.wen, 1)
    poke(p.addr, i)
    poke(p.wdata, i)
    step(1)
    i = i + 1
  }

  // Read it back                                                                                             
  i = 0
  for (p <- c.io.rports) {
    poke(p.addr, i)
    step(1)
    expect(p.rdata, i)
    i = i + 1
  }
}

object TestMem {
  def main(args: Array[String]): Unit = {
    //chiselMainTest(Array[String]("--backend", "v", "--genHarness"),                                         
    chiselMainTest(args,
      () => Module(new MultiPortedMem(1,1,1,128,32))){c => new TestMultiPortedMem(c)}
  }
}

Generated Verilog:

module test;                                                                                                  
  reg [0:0] io_enable;                                                                                        
  reg [6:0] io_rports_0_addr;                                                                                 
  reg [31:0] io_wports_0_wdata;                                                                               
  reg [6:0] io_wports_0_addr;                                                                                 
  reg [0:0] io_wports_0_wen;                                                                                  
  reg [6:0] io_rwports_0_addr;                                                                                
  reg [31:0] io_rwports_0_wdata;                                                                              
  reg [0:0] io_rwports_0_wen;                                                                                 
  wire [31:0] io_rports_0_rdata;                                                                              
  wire [31:0] io_rwports_0_rdata;                                                                             
  reg clk = 0;                                                                                                
  parameter clk_length = `CLOCK_PERIOD;                                                                       
  always #clk_length clk = ~clk;                                                                              
  /*** DUT instantiation ***/                                                                                 
    MultiPortedMem                                                                                            
      MultiPortedMem(                                                                                         
        .clk(clk),                                                                                            
        .io_enable(io_enable),                                                                                
        .io_rports_0_addr(io_rports_0_addr),                                                                  
        .io_wports_0_wdata(io_wports_0_wdata),                                                                
        .io_wports_0_addr(io_wports_0_addr),                                                                  
        .io_wports_0_wen(io_wports_0_wen),                                                                    
        .io_rwports_0_addr(io_rwports_0_addr),                                                                
        .io_rwports_0_wdata(io_rwports_0_wdata),                                                              
        .io_rwports_0_wen(io_rwports_0_wen),                                                                  
        .io_rports_0_rdata(io_rports_0_rdata),                                                                
        .io_rwports_0_rdata(io_rwports_0_rdata)                                                               
 );                                                                                                           

  /*** resets &&  VCD / VPD dumps ***/                                                                        
  initial begin                                                                                               
  end                                                                                                         

  task check_value;                                                                                           
    input [255:0] data;                                                                                       
    input [255:0] expected;                                                                                   
    begin                                                                                                     
      if (data == expected)                                                                                   
        $display("PASS");                                                                                     
      else                                                                                                    
        $display("FAIL");                                                                                     
    end                                                                                                       

  endtask                                                                                                     

  always @(posedge clk) begin                                                                                 
      $display("MultiPortedMem.io_rwports_0_rdata: 0x%x,  MultiPortedMem.io_rports_0_rdata: 0x%x, ", io_rports_0_rdata, io_rwports_0_rdata);                                                                                   
  end                                                                                                         

endmodule

afmagyar · Accepted Answer · 2014-09-26 15:47:33Z

5

Chisel 2.10 is too old to support the --genHarness option. Since it is a feature that is still somewhat under development, there is no warning about an invalid flag. You'll want to use Chisel 2.18 to get correct behavior from --genHarness.

A new release on Sonatype will be coming quite soon, which will bring the numbered releases to the current state of the head of Chisel's Git master.

In general, however, the --genHarness option does not support generating logic that performs the function of the tester. Instead, it generates a Verilog testbench that takes encoded command-line inputs that allow modifying the simulation values of top-level I/Os and state elements.

This generated tester is run in a VCS process spawned by the Chisel tester, which then sends its peek, poke, and step commands to VCS via IPC. Since the testbench generated by --genHarness is designed to accept these inputs, the Verilog instance of the DUT can be tested as it was with C++ simulation.

While it would theoretically be possible to have a framework for generating standalone Verilog testers encoding some of the logic in a Tester-extending class, it would require embedding the behavior of a Scala program in simulation Verilog, which is a significantly harder solution than the existing use of IPC for --genHarness.

answered Sep 26, 2014 at 15:47

afmagyar

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2 Comments

Mike N. Over a year ago

Thank you for the answer. The IPC mechanism makes sense. I had not really considered the implications of my expectations. :) While VCS is a clear choice to support... is there a path to using alternative verilog simulators?

afmagyar Over a year ago

That could be supported with some kind of '--verilogSim <x>' flag. Something we'll discuss for future releases.

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