Is there a simple example of how to generate verilog from Chisel3 module?

Question

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.

I take Gcd source code given on official web page of chisel.

  import chisel3._

  class GCD extends Module {
    val io = IO(new Bundle {
      val a  = Input(UInt(32.W))
      val b  = Input(UInt(32.W))
      val e  = Input(Bool())
      val z  = Output(UInt(32.W))
      val v  = Output(Bool())
    })
    val x = Reg(UInt(32.W))
    val y = Reg(UInt(32.W))
    when (x > y) {
      x := x -% y
    }.otherwise {
      y := y -% x
    }
    when (io.e) {
      x := io.a
      y := io.b
    }
    io.z := x
    io.v := y === 0.U
  }

I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.

Jack Koenig · Accepted Answer · 2022-05-18 18:19:44Z

15

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.13.8"

addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.3"

Put the above GCD source code in GCD.scala and add the following to the file:

import chisel3.stage.ChiselStage

object GCDDriver extends App {
  (new ChiselStage).emitVerilog(new GCD, args)
}

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory.

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory

edited May 18, 2022 at 18:19

answered Nov 7, 2016 at 21:28

Jack Koenig

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6 Comments

FabienM Over a year ago

Thanks jkoenig. Yes I seen the template repo, but I wanted a fast example to see how verilog was generated.

Matt Over a year ago

I tried to use the same code for generating a verilog code, but I get java.lang.ClassNotFoundException

Jack Koenig Over a year ago

Can you provide more of the error message? What class is it saying it cannot find?

Matt Over a year ago

Sorry for my very late reply. I just saw that I forgot to answer your question. I simply had to run sbt run to generate the Verilog code.

rhysd Over a year ago

Modifying above code to (new ChiselStage).emitVerilog(new GCD, args) and sbt "run --help" worked for me.

|

简悦 · Accepted Answer · 2022-09-09 14:46:57Z

1

You can use jupyter to generate Verilog code conveniently, just like in the Chisel bootcamp. Create a .ipynb file with scala kernel and run the setup code first:

import $ivy.`edu.berkeley.cs::chisel3:3.+`
import $plugin.$ivy.`edu.berkeley.cs:::chisel3-plugin:3.+`
import chisel3._

then you can generate Verilog code using chisel3.getVerilogString:

class Passthrough extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(4.W))
    val out = Output(UInt(4.W))
  })
  io.out := io.in
}

println(getVerilogString(new Passthrough))

answered Sep 9, 2022 at 14:46

简悦

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Comments

Alexy Khilaev · Accepted Answer · 2023-05-05 07:47:33Z

It is 2023, May, and i use next construction - build.sbt:

name := "example"    
version := "0.1"    
scalaVersion := "2.13.10"    
val chiselVersion = "3.6.0"    
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)    
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % chiselVersion

example.scala:

import chisel3._
import chisel3.stage.ChiselStage


class SimpleCounter(width: Int = 32) extends Module {
  val io = IO(new Bundle {
    val enable = Input(Bool())
    val out = Output(UInt(width.W))
  })

  val counter = RegInit(0.U(width.W))

  io.out <> counter

  when(io.enable) {
    counter := counter + 1.U
  }
}

object SimpleCounter extends App
{
    (new ChiselStage).emitVerilog(new SimpleCounter)
}

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