5

What is the simplest way to generate Verilog code from existing Chisel code?

Would i have to create my own build file?

For example from a standalone scala file (AND.scala) like the following one..

import Chisel._

class AND extends Module {
  val io = IO(new Bundle {
    val a = Bool(INPUT)
    val b = Bool(INPUT)
    val out = Bool(OUTPUT)
  })
  io.out := io.a & io.b
}

I have the complete Chisel3 Toolchain installed under ubuntu 16.4.

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1 Answer 1

7

See answer here: Is there a simple example of how to generate verilog from Chisel3 module?

In short, create a build.sbt file at the root of your project with the following in it:

scalaVersion := "2.12.13"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4"

Add this code to AND.scala

object ANDDriver extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(new AND, args)
}

Type sbt run on the command line at the root of your project.

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5 Comments

Thank you very much for the quick answer! Guess i oversaw the other thread. I just tried it and it works. NOTE: jdk8 and sbt have to be installed for this to work! (jdk9 did not work for me)
Anyway to generate verilog to a "target folder" instead of the same place as build.sbt?
Yep! Chisel and FIRRTL have command-line options. Notice how we pass args to chisel3.Driver.execute? We are propagating the command-line arguments sent to ANDDriver to Chisel. You can pass arguments like so: sbt "run --help". The specific one for "target folder" is --target-dir or -td, ie. sbt "run -td my_target_dir
chisel3.Driver is deprecated. Can you update this answer?
Done, thanks for the ping!

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